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clock aliases: add check through all clock aliases when getting clocks #1380

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merged 2 commits into from
Jul 3, 2020

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acomodi
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@acomodi acomodi commented Jun 25, 2020

Signed-off-by: Alessandro Comodi acomodi@antmicro.com

Description

This PR fixes the clock net aliasing for SDC commands other than create_clock

Related Issue

#1379

Motivation and Context

Clock aliases need to be used for other SDC commands and not only create_clock.

How Has This Been Tested?

I have added a regression test that uses set_max_delay sdc constraint

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@probot-autolabeler probot-autolabeler bot added lang-cpp C/C++ code lang-netlist tests VPR VPR FPGA Placement & Routing Tool VTR Flow VTR Design Flow (scripts/benchmarks/architectures) labels Jun 25, 2020
@acomodi acomodi force-pushed the fix-net-aliases branch 2 times, most recently from 05cf7c0 to 1516b6c Compare June 25, 2020 10:30
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
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@vaughnbetz vaughnbetz left a comment

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Looks good. Thanks.

@kmurray
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kmurray commented Jul 3, 2020

Looks good to me too.

@kmurray kmurray merged commit 86fc164 into verilog-to-routing:master Jul 3, 2020
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3 participants