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Add extended lookahead map #1449

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acomodi
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@acomodi acomodi commented Jul 23, 2020

Description

This PR adds a new lookahead map method called extended map. This new kind of lookahead takes the same mechanisms of generation of the cost map as found in the connection box based lookahead currently implemented in the SymbiFlow/VTR fork, and uses the OPIN -> CHAN and CHAN -> IPIN delay information from the upstream lookahead map.

This PR includes new code to perform the node sampling which is more robust with respect to the current implementation, but takes more time to compute, hence the need of parallelize the graph exploration to fill the map costs.

Even with parallelization, though, the lookahead generation takes too long for the current regression tests in VTR, therefore the choice of adding a completely new lookahead type (extended map), so not to interfere with the current implementation.

Related Issue

There is no issue currently open, but this PR is one of the last ones needed to fully upstream the SymbiFlow/VTR fork's changes needed to perform P&R using upstream VTR for 7-series devices.

Motivation and Context

The current lookahead map implementation is not sufficient to provide accurate estimates during the router expansions for 7-Series devices. This results in high run-times with bad CPD results. To achieve better results, the lookahead build strategy needed to be improved (at least for 7-series).

How Has This Been Tested?

The new lookahead has been tested on SymbiFlow architectures: the issue keeping track of the progress is this one

Types of changes

  • Bug fix (change which fixes an issue)
  • New feature (change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to change)

Checklist:

  • My change requires a change to the documentation
  • I have updated the documentation accordingly
  • I have added tests to cover my changes
  • All new and existing tests passed

@probot-autolabeler probot-autolabeler bot added build Build system lang-cpp C/C++ code lang-make CMake/Make code VPR VPR FPGA Placement & Routing Tool labels Jul 23, 2020
@acomodi acomodi requested review from vaughnbetz, litghost and HackerFoo and removed request for HackerFoo July 23, 2020 14:09
@probot-autolabeler probot-autolabeler bot added the libarchfpga Library for handling FPGA Architecture descriptions label Jul 27, 2020
@acomodi acomodi force-pushed the add-extended-lookahead-map branch from 6586087 to 88b5632 Compare July 27, 2020 19:46
@acomodi acomodi changed the title Add extended lookahead map WIP: Add extended lookahead map Jul 27, 2020
@vaughnbetz
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Not sure what all the failures are due to -- rerun?

@vaughnbetz
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Looks like at least some of these failures are due to failures in the new lookahead builder.

@acomodi
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acomodi commented Aug 4, 2020

I have restored the changes to only add the extended lookahead map. Turns out that, even with the bugfix of the CHANX/CHANY that got merged together, CPD and in general QoR seems to be worsening also for the strong regression tests.

The problem is that the lookahead map and the extended lookahead map use two very different methods of both generating and querying the cost map.

I am unsure whether the two methods can be merged together safely and preserve the QoR of vtr regression tests, as well as run-time.

@acomodi acomodi changed the title WIP: Add extended lookahead map Add extended lookahead map Aug 10, 2020
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acomodi commented Aug 11, 2020

I believe this is ready for review at the current state.

I have exported some of the code from the lookahead map in the lookahead_map_utils file as it could be shared with the extended map code.

This implementation does not interfere with the regression tests as they all use the map lookahead.
I might as well add some tests which do make use of the extended map to test its behaviour and avoid regressions as well.

@probot-autolabeler probot-autolabeler bot added the VTR Flow VTR Design Flow (scripts/benchmarks/architectures) label Aug 11, 2020
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acomodi commented Aug 11, 2020

@vaughnbetz @litghost @HackerFoo FYI, I think this PR is ready for a first review iteration

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LGTM

@acomodi acomodi force-pushed the add-extended-lookahead-map branch 2 times, most recently from a8e9b8c to 53bfad8 Compare September 10, 2020 17:22
  - New sampling method for lookahead map.
  - New spiral hole filling algorithm
  - Use a lightweight version of PQ_Entry (PQ_Entry_Lite)
  - Use maps in run_dijkstra()
  - Move context of router_lookahead_map_utils inside of util
    namespace.
  - Parallelization of lookahead generation

lookahead: add new extended map lookahead

This lookahead generates a map with a more complex and complete way of
sampling and expanding the nodes to reach all destinations.

The dijkstra expansion is parallelized to overcome the higher number of
samples needed.

It also adds a penalty cost factor based on distance between the origin
and destination nodes.

extended_lookahead: cleaned code and reduced code duplication

Signed-off-by: Dusty DeWeese <dustin.deweese@gmail.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
- The cost map filling routine has been simplified and the relevant code
extracted in two different sub-routines (penalty calculation, cost
filling)
- Commented used Doxygen compatible style some of the important methods
and class members

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
- Added better description on the user options
- Added test with random_shuffle nodes reordering

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
@acomodi
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acomodi commented Sep 11, 2020

@vaughnbetz I have rebased and solved all the conflicts due to the RCV merge

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vaughnbetz commented Sep 11, 2020

Thanks @acomodi . There are a few unresolved conversations, requests.

  1. Can you go through and comment on them: either change (mostly commenting and changing to RRNodeIDs) or make a new PR/issue to track those updates so we don't lose them?
  2. Waiting for kokoro to finish.

@acomodi : if you can do 1 (comment / transfer to new PR or issue) while we're waiting for 2 (kokoro) then I can merge once kokoro finishes.

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acomodi commented Sep 11, 2020

@vaughnbetz Ok, I will open a new PR based on this one to add the additional comments and the assertion, as well as opening the issues.

I do not have time unfortunately to update the RRNodeId today, but I can open an issue about it as well

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acomodi commented Sep 11, 2020

Opened issues:

@vaughnbetz vaughnbetz merged commit 95843c2 into verilog-to-routing:master Sep 11, 2020
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Thanks @acomodi. This is a major PR !
Tracking the remaining nits / cleanups with other issues sounds good.
Merged.

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