Updating router lookahead

[amin1377]

In this pull request, we have optimized the memory footprint and reduced the build time of the router lookahead by adopting a strategy that involves fewer samples during the construction process. The previous implementation stored the cost to reach each dx and dy, which has now been replaced with a more efficient approach that samples a reduced number of points on the chip.

This got bigger:

• Fixed a bug where the router lookahead Djikstra flood had "holes" (zero cost estimates) in a few places due to not finding any IPIN at the relevant (dx,dy). Now we fill in those 0 entries with the average over a 3x3 window of nearby (dx,dy) values.
• Added a new place_delay_model (simple place delay model) which gets the minimum delay for each (dx,dy) by post-processing the router lookahead data. This simplifies code paths and greatly reduces place_delay_matrix compute time.

[amin1377]

QoR on large VTR benchmark:
.
These results are with default settings, so they do not include the simple place delay matrix. They do include hole filling in the router lookahead or the sparsification of the router lookahead data strucutres.

[amin1377]

QoR on Titan benchmark:

[vaughnbetz]

One QoR failure (too good):
19:29:43 | k6_frac_N10_frac_chain_mem32K_40nm.xml/LU8PEEng.v/common min_chan_width_route_time relative value 0.09854500000000001 outside of range [0.1,15.0], above absolute threshold 2.0 and not equal to golden value: 4000.0
19:29:43 | regression_tests/vtr_reg_nightly_test3_odin/vtr_reg_qor...[Pass]

Just needs an updated golden.

As a follow-up, you should make a PR to enable the new placer delay matrix ASAP as the results are good and we don't want anyone to break it. That PR should include VTR, Titan and Koios QoR results.

[vaughnbetz]

Thanks!
Some commenting suggestions and this is a good opportunity to make Doxygen documentation on the VTR web page for the router lookahead.