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Add indentation ignoring to multiline macros or specific regexp
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Original file line number | Diff line number | Diff line change |
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// Issue 1082 | ||
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`define drive_agt(AGT_ID) \ | ||
begin \ | ||
some_agt_seq seq; \ | ||
seq = some_agt_seq::type_id::create \ | ||
(.name({"some_agt_seq_",$sformatf("%0d", AGT_ID)}), \ | ||
.contxt(get_full_name())); \ | ||
seq.start(env.adc_agt[AGT_ID].sqr_l1); \ | ||
end | ||
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`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
// Indentation should also ignore multiline macros with trailing whitespaces | ||
`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
// Some example module to check that the rest of indentation works fine | ||
module ram_controller (); | ||
ram_sp_sr_sw #( | ||
.DATA_WIDTH(16), | ||
.ADDR_WIDTH(8), | ||
.RAM_DEPTH(256) | ||
) ram ( | ||
clk, | ||
address, | ||
data, | ||
cs, | ||
we, | ||
oe | ||
) | ||
; | ||
endmodule | ||
// Local Variables: | ||
// verilog-indent-ignore-multiline-macros: t | ||
// End: |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,42 @@ | ||
// Ignore indentation for outshine header lines that start with // * | ||
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// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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// Some example module to check that the rest of indentation works fine | ||
module ram_controller (); | ||
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ram_sp_sr_sw #( | ||
.DATA_WIDTH(16), | ||
.ADDR_WIDTH(8), | ||
.RAM_DEPTH(256) | ||
) ram ( | ||
clk, | ||
address, | ||
data, | ||
cs, | ||
we, | ||
oe | ||
) | ||
; | ||
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endmodule | ||
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// Local Variables: | ||
// verilog-indent-ignore-regexp: "// \\*" | ||
// End: |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,59 @@ | ||
// Issue 1082 | ||
|
||
`define drive_agt(AGT_ID) \ | ||
begin \ | ||
some_agt_seq seq; \ | ||
seq = some_agt_seq::type_id::create \ | ||
(.name({"some_agt_seq_",$sformatf("%0d", AGT_ID)}), \ | ||
.contxt(get_full_name())); \ | ||
seq.start(env.adc_agt[AGT_ID].sqr_l1); \ | ||
end | ||
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||
|
||
`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
// Indentation should also ignore multiline macros with trailing whitespaces | ||
`define foo(ARG) \ | ||
begin \ | ||
$display(\"Bar\"); \ | ||
$display(\"Baz\"); \ | ||
end | ||
// Some example module to check that the rest of indentation works fine | ||
module ram_controller (); | ||
ram_sp_sr_sw #( | ||
.DATA_WIDTH(16), | ||
.ADDR_WIDTH(8), | ||
.RAM_DEPTH(256) | ||
) ram ( | ||
clk, | ||
address, | ||
data, | ||
cs, | ||
we, | ||
oe | ||
) | ||
; | ||
endmodule | ||
// Local Variables: | ||
// verilog-indent-ignore-multiline-macros: t | ||
// End: |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,42 @@ | ||
// Ignore indentation for outshine header lines that start with // * | ||
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// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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||
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// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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||
// * Header1 | ||
// * Header2 | ||
// * Header3 | ||
// ** SubHeader3 | ||
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||
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// Some example module to check that the rest of indentation works fine | ||
module ram_controller (); | ||
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||
ram_sp_sr_sw #( | ||
.DATA_WIDTH(16), | ||
.ADDR_WIDTH(8), | ||
.RAM_DEPTH(256) | ||
) ram ( | ||
clk, | ||
address, | ||
data, | ||
cs, | ||
we, | ||
oe | ||
) | ||
; | ||
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||
endmodule | ||
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// Local Variables: | ||
// verilog-indent-ignore-regexp: "// \\*" | ||
// End: |
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