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Add indentation ignoring to multiline macros or specific regexp
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gmlarumbe committed Jun 26, 2022
1 parent ef566ce commit 5b9bc2a
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4 changes: 4 additions & 0 deletions tests/indent_macro_comment.v
Expand Up @@ -39,3 +39,7 @@
// the indentation this time; but the indentation
// returned to (v2) as set by that sign in `define TEMPB
`endif

// Local Variables:
// verilog-indent-ignore-multiline-macros: nil
// End:
59 changes: 59 additions & 0 deletions tests/indent_macro_ignore_multiline.sv
@@ -0,0 +1,59 @@
// Issue 1082

`define drive_agt(AGT_ID) \
begin \
some_agt_seq seq; \
seq = some_agt_seq::type_id::create \
(.name({"some_agt_seq_",$sformatf("%0d", AGT_ID)}), \
.contxt(get_full_name())); \
seq.start(env.adc_agt[AGT_ID].sqr_l1); \
end


`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
// Indentation should also ignore multiline macros with trailing whitespaces
`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
// Some example module to check that the rest of indentation works fine
module ram_controller ();
ram_sp_sr_sw #(
.DATA_WIDTH(16),
.ADDR_WIDTH(8),
.RAM_DEPTH(256)
) ram (
clk,
address,
data,
cs,
we,
oe
)
;
endmodule
// Local Variables:
// verilog-indent-ignore-multiline-macros: t
// End:
42 changes: 42 additions & 0 deletions tests/indent_macro_ignore_regexp.sv
@@ -0,0 +1,42 @@
// Ignore indentation for outshine header lines that start with // *

// * Header1
// * Header2
// * Header3
// ** SubHeader3


// * Header1
// * Header2
// * Header3
// ** SubHeader3

// * Header1
// * Header2
// * Header3
// ** SubHeader3


// Some example module to check that the rest of indentation works fine
module ram_controller ();

ram_sp_sr_sw #(
.DATA_WIDTH(16),
.ADDR_WIDTH(8),
.RAM_DEPTH(256)
) ram (
clk,
address,
data,
cs,
we,
oe
)
;

endmodule


// Local Variables:
// verilog-indent-ignore-regexp: "// \\*"
// End:
1 change: 1 addition & 0 deletions tests/label_macro.v
Expand Up @@ -20,4 +20,5 @@ endclass
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// verilog-indent-ignore-multiline-macros: nil
// End:
4 changes: 4 additions & 0 deletions tests_ok/indent_macro_comment.v
Expand Up @@ -39,3 +39,7 @@
// the indentation this time; but the indentation
// returned to (v2) as set by that sign in `define TEMPB
`endif

// Local Variables:
// verilog-indent-ignore-multiline-macros: nil
// End:
59 changes: 59 additions & 0 deletions tests_ok/indent_macro_ignore_multiline.sv
@@ -0,0 +1,59 @@
// Issue 1082

`define drive_agt(AGT_ID) \
begin \
some_agt_seq seq; \
seq = some_agt_seq::type_id::create \
(.name({"some_agt_seq_",$sformatf("%0d", AGT_ID)}), \
.contxt(get_full_name())); \
seq.start(env.adc_agt[AGT_ID].sqr_l1); \
end


`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
// Indentation should also ignore multiline macros with trailing whitespaces
`define foo(ARG) \
begin \
$display(\"Bar\"); \
$display(\"Baz\"); \
end
// Some example module to check that the rest of indentation works fine
module ram_controller ();
ram_sp_sr_sw #(
.DATA_WIDTH(16),
.ADDR_WIDTH(8),
.RAM_DEPTH(256)
) ram (
clk,
address,
data,
cs,
we,
oe
)
;
endmodule
// Local Variables:
// verilog-indent-ignore-multiline-macros: t
// End:
42 changes: 42 additions & 0 deletions tests_ok/indent_macro_ignore_regexp.sv
@@ -0,0 +1,42 @@
// Ignore indentation for outshine header lines that start with // *

// * Header1
// * Header2
// * Header3
// ** SubHeader3


// * Header1
// * Header2
// * Header3
// ** SubHeader3

// * Header1
// * Header2
// * Header3
// ** SubHeader3


// Some example module to check that the rest of indentation works fine
module ram_controller ();

ram_sp_sr_sw #(
.DATA_WIDTH(16),
.ADDR_WIDTH(8),
.RAM_DEPTH(256)
) ram (
clk,
address,
data,
cs,
we,
oe
)
;

endmodule


// Local Variables:
// verilog-indent-ignore-regexp: "// \\*"
// End:
1 change: 1 addition & 0 deletions tests_ok/label_macro.v
Expand Up @@ -20,4 +20,5 @@ endclass // c
// Local Variables:
// verilog-minimum-comment-distance: 1
// verilog-auto-endcomments: t
// verilog-indent-ignore-multiline-macros: nil
// End:
33 changes: 33 additions & 0 deletions verilog-mode.el
Expand Up @@ -679,6 +679,18 @@ Set to 0 to have all directives start at the left side of the screen."
:type 'integer)
(put 'verilog-indent-level-directive 'safe-local-variable #'integerp)

(defcustom verilog-indent-ignore-multiline-macros t
"Non-nil means ignore indentation on lines that are part of a multiline macro."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-ignore-multiline-macros 'safe-local-variable #'verilog-booleanp)

(defcustom verilog-indent-ignore-regexp nil
"Regexp that matches lines that should be ignored for indentation."
:group 'verilog-mode-indent
:type 'boolean)
(put 'verilog-indent-ignore-regexp 'safe-local-variable #'stringp)

(defcustom verilog-cexp-indent 2
"Indentation of Verilog statements split across lines."
:group 'verilog-mode-indent
Expand Down Expand Up @@ -4015,6 +4027,10 @@ Variables controlling indentation/edit style:
function keyword.
`verilog-indent-level-directive' (default 1)
Indentation of \\=`ifdef/\\=`endif blocks.
`verilog-indent-ignore-multiline-macros' (default t)
Non-nil means ignore indentation on lines that are part of a multiline macro.
`verilog-indent-ignore-regexp' (default nil
Regexp that matches lines that should be ignored for indentation.
`verilog-cexp-indent' (default 1)
Indentation of Verilog statements broken across lines i.e.:
if (a)
Expand Down Expand Up @@ -6911,6 +6927,9 @@ Only look at a few lines to determine indent level."
(let ((type (car indent-str))
(ind (car (cdr indent-str))))
(cond
(; handle indentation ignoring
(verilog-indent-ignore-p)
nil)
(; handle continued exp
(eq type 'cexp)
(let ((here (point)))
Expand Down Expand Up @@ -7568,6 +7587,18 @@ Region is defined by B and ENDPOS."
(insert
(format "%s %d" type val))))

(defun verilog-indent-ignore-p ()
"Return non-nil if current line should ignore indentation."
(or (and verilog-indent-ignore-multiline-macros ; Ignore multiline macros
(or (looking-at ".*\\\\\\s-*$") ; Line with multiline define, ended in "\" or "\" + trailing whitespace
(save-excursion ; Last line after multiline define
(verilog-backward-syntactic-ws)
(unless (bobp)
(backward-char))
(looking-at "\\\\"))))
(and verilog-indent-ignore-regexp ; Ignore lines according to specified regexp
(looking-at verilog-indent-ignore-regexp))))


;;; Completion:
;;
Expand Down Expand Up @@ -15086,6 +15117,8 @@ Files are checked based on `verilog-library-flags'."
verilog-indent-begin-after-if
verilog-indent-class-inside-pkg
verilog-indent-declaration-macros
verilog-indent-ignore-multiline-macros
verilog-indent-ignore-regexp
verilog-indent-level
verilog-indent-level-behavioral
verilog-indent-level-declaration
Expand Down

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