Fix indentation following a more complete set of compiler directives,…

… bug 901.

	* verilog-mode.el (verilog-directive-re)
	(verilog-compiler-directives, verilog-keywords): Match full set of
	IEEE 2012-1800 compiler directives (plus some extras) when
	determining indentation, bug 901.  Reported by Bernd Beuster.

tests_ok/autoinput_none.v

@@ -1,19 +1,19 @@
 // Julian Gorfajn
 
 `default_nettype none
-  
-  module top
-    (
-     /*AUTOOUTPUT*/
-     // Beginning of automatic outputs (from unused autoinst outputs)
-     output wire o, // From sub of Sub.v
-     // End of automatics
-     // Beginning of automatic outputs (from unused autoinst outputs)
-     /*AUTOINPUT*/
-     // Beginning of automatic inputs (from unused autoinst inputs)
-     input wire  i                      // To sub of Sub.v
-     // End of automatics
-     );
+
+module top
+  (
+   /*AUTOOUTPUT*/
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   output wire o, // From sub of Sub.v
+   // End of automatics
+   // Beginning of automatic outputs (from unused autoinst outputs)
+   /*AUTOINPUT*/
+   // Beginning of automatic inputs (from unused autoinst inputs)
+   input wire  i                        // To sub of Sub.v
+   // End of automatics
+   );
 
    Sub sub (/*AUTOINST*/
             // Outputs

tests_ok/autowire_pkg_bug195.v

@@ -1,6 +1,6 @@
 `default_nettype none
-  
-  package testcase_pkg;
+
+package testcase_pkg;
 
    typedef int unsigned uint;
 

tests_ok/indent_preproc.v

@@ -2,26 +2,26 @@
 
 aa;
 `__FILE__
-  `__LINE__
-    `celldefine
-      `end_keywords
-        `resetall
-          `unconnected_drive
-            `undefineall
-              
+`__LINE__
+`celldefine
+`end_keywords
+`resetall
+`unconnected_drive
+`undefineall
+
 `ifdef AA
 `else
 `endif
 `ifndef AA
 `elsif FOO
 `endif
-              
-              `begin_keywords "FOO"
+
+`begin_keywords "FOO"
 `undef FOO
-
+  
 `line 2 "xx" 2
 `include "YY"
 `include <YY>
-  `pragma endofline
+`pragma endofline
 `timescale 10ns/10ps
 `define foo bar

verilog-mode.el

@@ -1924,14 +1924,22 @@ find the errors."
 (if (featurep 'xemacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-xemacs))
 (if (featurep 'emacs) (add-hook 'compilation-mode-hook 'verilog-error-regexp-add-emacs))
 
-(defconst verilog-directive-re
+(defconst verilog-compiler-directives
   (eval-when-compile
-    (verilog-regexp-words
-     '(
-   "`case" "`default" "`define" "`else" "`elsif" "`endfor" "`endif"
-   "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
-   "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
-   "`time_scale" "`undef" "`while" ))))
+    '( ;; compiler directives, from IEEE 1800-2012 section 22.1
+    "`__FILE__" "`__LINE" "`begin_keywords" "`celldefine" "`default_nettype"
+    "`define" "`else" "`elsif" "`end_keywords" "`endcelldefine" "`endif"
+    "`ifdef" "`ifndef" "`include" "`line" "`nounconnected_drive" "`pragma"
+    "`resetall" "`timescale" "`unconnected_drive" "`undef" "`undefineall"
+     ;; compiler directives not covered by IEEE 1800
+     "`case" "`default" "`endfor" "`endprotect" "`endswitch" "`endwhile" "`for"
+     "`format" "`if" "`let" "`protect" "`switch" "`timescale" "`time_scale"
+     "`while"
+     ))
+  "List of Verilog compiler directives.")
+
+(defconst verilog-directive-re
+  (verilog-regexp-words verilog-compiler-directives))
 
 (defconst verilog-directive-re-1
   (concat "[ \t]*"  verilog-directive-re))
@@ -2856,11 +2864,8 @@ find the errors."
      )))
 
 (defconst verilog-keywords
-  '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
-     "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
-     "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
-     "`time_scale" "`undef" "`while"
-
+  (append verilog-compiler-directives
+   '(
      "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
      "assert" "assign" "assume" "automatic" "before" "begin" "bind"
      "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
@@ -2902,7 +2907,7 @@ find the errors."
      "sync_reject_on" "unique0" "until" "until_with" "untyped" "weak"
      ;; 1800-2012
      "implements" "interconnect" "nettype" "soft"
-     )
+     ))
   "List of Verilog keywords.")
 
 (defconst verilog-comment-start-regexp "//\\|/\\*"