Fix indentation of coverpoints (#1321) (#1766).

* verilog-mode.el (verilog-at-constraint-p): Fix indentation of coverpoints (#1321) (#1766). Signed-off-by: Gonzalo Larumbe <gonzalomlarumbe@gmail.com>
veripool · May 12, 2022 · 95df088 · 95df088
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commit 95df088
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diff --git a/tests_ok/indent_covergroup_swan.v b/tests_ok/indent_covergroup_swan.v
@@ -2,43 +2,43 @@ module m;
    bit [0:0] a, b, c;
    covergroup g;
       cp_ab: coverpoint {a,b} {
-                               bins one = {1};
-                               bins two = {2};
-                               }
-        
-        cp_ab_if_c: coverpoint {a,b} iff c {
-           bins one = {1};
-           bins two = {2};
-        }
-        
-        cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
-                                                     bins one = {1};
-                                                     bins two = {2};
-                                                     }
-          
-          cp_a_if_bc: coverpoint {a,b} iff {b,c} {
-                                                  bins one = {1};
-                                                  bins two = {2};
-                                                  }
-            
-            cp_a_slice : coverpoint a[0] {
-                                          bins one = {1};
-                                          bins two = {2};
-                                          }
-              
-              cp_a_slice_if_b : coverpoint a[0] iff b {
-                 bins one = {1};
-                 bins two = {2};
-              }
-              
-              cp_a_if_b_slice : coverpoint a iff b[0] {
-                                                       bins one = {1};
-                                                       bins two = {2};
-                                                       }
-                
-                cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
-                                                                  bins one = {1};
-                                                                  bins two = {2};
-                                                                  }
-                  endgroup
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_ab_if_c: coverpoint {a,b} iff c {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_ab_if_c_slice: coverpoint {a,b} iff c[0] {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_a_if_bc: coverpoint {a,b} iff {b,c} {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_a_slice : coverpoint a[0] {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_a_slice_if_b : coverpoint a[0] iff b {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_a_if_b_slice : coverpoint a iff b[0] {
+         bins one = {1};
+         bins two = {2};
+      }
+
+      cp_a_slice_if_b_slice : coverpoint a[0] iff b[0] {
+         bins one = {1};
+         bins two = {2};
+      }
+   endgroup
 endmodule
diff --git a/verilog-mode.el b/verilog-mode.el
@@ -6646,7 +6646,7 @@ Also move point to constraint."
                        ))
             ;; if first word token not keyword, it maybe the instance name
             ;;   check next word token
-            (if (looking-at "\\<\\w+\\>\\|\\s-*(\\s-*\\S-+")
+            (if (looking-at "\\<\\w+\\>\\|\\s-*[\[(}]\\s-*\\S-+")
                 (progn (verilog-beg-of-statement)
                        (if (and
                             (not (string-match verilog-named-block-re (buffer-substring pt (point)))) ;; Abort if 'begin' keyword is found