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Support For package item parameter declaration #39

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veripoolbot opened this issue Oct 23, 2008 · 1 comment
Closed

Support For package item parameter declaration #39

veripoolbot opened this issue Oct 23, 2008 · 1 comment
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@veripoolbot veripoolbot commented Oct 23, 2008


Author Name: Nicky Ayoub
Original Redmine Issue: 39 from https://www.veripool.org
Original Date: 2008-10-23
Original Assignee: Wilson Snyder (@wsnyder)


This one is iffy. I created a quick patch to support a module I have with package scoped parameters.

[nicky@loki Verilog-Perl]$ cat verilog/v_param.v 

parameter MOST_SIG_BIT = 7;
parameter LEAST_SIG_BIT = 0;

module testcase (
output logic [MOST_SIG_BIT:LEAST_SIG_BIT] data,
            output logic       data_rdy,
            input              serial_in
           );

endmodule

The patch is extremely simple and does not handle the full set of SV productions that are needed.
I created a @packageItem@ production that points to @varDecl@. It's probably not compliant but "it works for me".
Looking at the grammar in the spec, this solution looks to be subset so I think it's safe but not complete. I will go through it more closely in the morning. Hopefully the patch lets you see where I am going with this.

As always, any pointers are appreciated!

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@veripoolbot veripoolbot commented Nov 7, 2008


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2008-11-07T16:40:04Z


IMHO I think global variables were a really bad addition as it restricts IP reuse... But that doesn't change that it's valid code ;(

Anyhow, committed to git. I plan on pushing a release Monday including this unless something else comes up.

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