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Author Name: elaine li
Original Redmine Issue: 869 from https://www.veripool.org
Original Date: 2015-01-08
I create a new pin of the cell use the $cell->new_pins, then i want to get the modified rtl,and all the content except the new pin not changed(include the always block)。
I use the $netlist->verilog_text,and what I get is not complate,it's not include the always block.
The text was updated successfully, but these errors were encountered:
Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-01-12T13:04:56Z
verilog_text only works on gate-style netlists. If you want to preserve the rest you'll need to perform text-style replacements, or use a technique similar to vpassert (in the distribution .tar.gz file).
Author Name: elaine li
Original Redmine Issue: 869 from https://www.veripool.org
Original Date: 2015-01-08
I create a new pin of the cell use the $cell->new_pins, then i want to get the modified rtl,and all the content except the new pin not changed(include the always block)。
I use the $netlist->verilog_text,and what I get is not complate,it's not include the always block.
The text was updated successfully, but these errors were encountered: