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VLIW architecture is an appropriate alternative for exploiting instruction-level parallelism (ILP) in programs. In this project 5 stage pipline and 6 functional unit is used.

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vgupta32333/VLIW-Architecture

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Instruction codes are given as a text file, task is to read them using python and get results.

demo main memory has been created as 'memory.txt' file, value of registers are given there.

Name - Virat Gupta

CA PROJECT CODE...

Instruction to be run are available in "instructions.txt" file.

[Note] Don't give extra line break space at the end in "instructions.txt" file otherwise it will give "index out of range error".

Steps to run the Code.

  1. Run the file named "generateBin.py" (It will create a Binary file of instructions)
  2. Now run the file "createTestBench.py" (It will run the instructions and show output in terminal)

Thank You.....

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VLIW architecture is an appropriate alternative for exploiting instruction-level parallelism (ILP) in programs. In this project 5 stage pipline and 6 functional unit is used.

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