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m68k: fix use of unitialised temp reg in ASL #7

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6dd2a04
linux-user: Signals processing is not thread-safe.
Mar 21, 2011
351f13e
linux-user: define default cpu model in configure instead of linux-us…
vivier Jul 27, 2011
3dfdc9f
linux-user: specify the cpu model during configure
vivier Jul 27, 2011
cb5af3f
linux-user,m68k: display default cpu
vivier Jul 28, 2011
07bf5e6
linux-user,arm: display default cpu
vivier Mar 15, 2012
298920c
linux-user: allow mount to work again on m68k (and others ?)
vivier Feb 18, 2012
ab1ebd3
linux-user: correctly align types in thunking code
vivier Dec 5, 2012
91b85cc
linux-user: on m68k, set d_off of getdents64() to 0
vivier Dec 16, 2012
26a55f6
linux-user: add socketcall() strace
vivier Dec 25, 2012
65b3c3f
linux-user: correct setsockopt() strace.
vivier Dec 29, 2012
2005a2f
linux-user: Add oldumount syscall
vivier Jan 2, 2013
783573b
linux-user: add socket() strace
vivier Jan 3, 2013
5b9cd70
arm: add missing TARGET_O_*
vivier Feb 2, 2013
6efc0c8
linux-user: SH-4 long long alignment is 4
vivier Nov 19, 2015
7516e92
linux-user: in SH-4 sigaltstack, ss_flags is int.
vivier Nov 19, 2015
b92faeb
linux-user: allow to put strace into a file
vivier Dec 3, 2015
742e375
linux-user: use target_to_host_sigset()
vivier Dec 4, 2015
92f75e1
linux-user,m68k: manage EXCP_DIV0
vivier Dec 27, 2015
c441a7b
linux-user: add rtnetlink(7) support
vivier Jun 4, 2015
3487d60
linux-user: support netlink protocol NETLINK_KOBJECT_UEVENT
vivier Jun 5, 2015
ed184a8
linux-user: add netlink audit
vivier Jul 14, 2015
db0ae83
linux-user: add partial SOL_NETLINK level in setsockopt()/getsockopt()
vivier Feb 5, 2016
8427d68
linux-user: update get_thread_area/set_thread_are strace
vivier Feb 6, 2016
d0e4a87
linux-user: add option to intercept execve() syscalls
Jan 27, 2016
968801c
linux-user: define O_ACCMODE, RDONLY, WRONLY, RDWR for target ppc
vivier Mar 24, 2015
a0a9b29
linux-user: epoll_ctl(), epoll_wait(), opaque must stay opaque
vivier Jun 26, 2015
fd1b36b
linux-user: add lock around g_posix_timers array
vivier Jun 26, 2015
5c385fb
linux-user: fix clone() strace
vivier Feb 13, 2016
22c7990
linux-user: Fix qemu-binfmt-conf.h to store config across reboot
vivier Jan 28, 2016
679d35b
target-m68k: update binfmts m68k mask to ignore OS ABI
vivier Feb 4, 2016
554ad28
linux-user: synchronize FUTEX_WAKE_OP with atomic operation
vivier Feb 13, 2016
2bf13b3
fpu: define floatx80_e, floatx80_log2e and floatx80_10
vivier Jan 21, 2013
facea34
fpu: define floatx80_default_inf
vivier Jan 21, 2013
59eb1c7
scripts: create a template to use with lxc-create
vivier Feb 3, 2013
c627fa8
scripts: add a script to compile qemu and run lxc-create -t lxc-cross…
vivier Jan 14, 2013
b2475bd
m68k: define m680x0 CPUs and features
vivier May 10, 2009
aac86e6
m68k: add missing accessing modes for some instructions.
vivier May 9, 2009
0361b74
m68k: add Motorola 680x0 family common instructions.
vivier May 18, 2009
0ee93c5
m68k: add Scc instruction with memory operand.
vivier May 18, 2009
97feefa
m68k: add DBcc instruction.
vivier May 18, 2009
3ec9e8f
m68k: modify movem instruction to manage word
vivier May 18, 2009
19fab2e
m68k: add 64bit divide.
vivier May 17, 2009
3fceb50
m68k: add 32bit and 64bit multiply
vivier May 18, 2009
5c89795
m68k: add word data size for suba/adda
vivier May 18, 2009
67611d6
m68k: add fpu
vivier May 18, 2009
bd1d721
m68k: add "byte", "word" and memory shift
vivier May 20, 2009
fca0e8a
m68k: add "byte", "word" and memory rotate.
vivier May 20, 2009
e758278
m68k: add bitfield_mem, bitfield_reg
vivier May 20, 2009
126e66e
m68k: add variable offset/width to bitfield_reg/bitfield_mem
vivier May 23, 2009
309d39b
m68k: add cas
vivier May 28, 2009
b9692d7
m68k: add cas
andreas-schwab May 30, 2009
a3303d6
m68k: define fcntl constants
andreas-schwab May 30, 2009
64e4747
m68k: add DBcc instruction.
andreas-schwab May 30, 2009
69c8b64
m68k: allow fpu to manage double data type.
vivier May 30, 2009
9d2828b
m68k: allow fpu to manage double data type with fmove to <ea>
vivier Jun 6, 2009
c1c7b8f
m68k: add FScc instruction
vivier May 31, 2009
df4cb7e
m68k: add single data type to gen_ea
vivier May 31, 2009
a7e1fc8
m68k: add linkl instruction
vivier Jun 4, 2009
5880eb3
m68k: Add fmovecr
vivier Jun 6, 2009
ab574ad
m68k: improve CC_OP_LOGIC
vivier Jun 13, 2009
afb8a0d
m68k: correct neg condition code flags computation
vivier Jun 13, 2009
dc58e82
m68k: add EA support for negx
vivier Jun 13, 2009
332c832
m68k: add abcd instruction
vivier Jun 14, 2009
b4cd887
m68k: add sbcd instruction
vivier Jun 14, 2009
883efd4
mm68k: add nbcd instruction
vivier Jun 14, 2009
a77d7c8
m68k: set X flag according size of operand
vivier Jun 14, 2009
f260712
m68k: on 0 bit shift, don't update X flag
vivier Jun 14, 2009
ec95144
m68k: improve addx instructions
vivier Jun 15, 2009
c73a261
m68k: improve subx,negx instructions
vivier Jun 15, 2009
8e479de
m68k: improve asl/asr
vivier Jun 16, 2009
d8786d8
m68k: use read_imm1() when it is possible
vivier Jun 16, 2009
32ae09e
m68k: correct shift side effect for roxrl and roxll
vivier Jun 24, 2009
884fbac
m68k: asl/asr, clear C flag if shift count is 0
vivier Jun 26, 2009
47a632c
m68k: lsl/lsr, clear C flag if shift count is 0
vivier Jun 26, 2009
9c92d85
m68k: correct divs.w and divu.w
vivier Jun 26, 2009
3cb9b3b
m68k: correct flags with negl
vivier Jun 26, 2009
374a98b
m68k: for bitfield opcodes, correct operands corruption
vivier Jun 27, 2009
e4bbcbd
m68k: Added ULL to 64 bit integer in helper.c
peterbjorgensen Apr 2, 2010
69edf57
m68k: Correct bfclr in register case.
vivier Apr 4, 2010
db535b0
m68k-linux-user: add '--enable-emulop'
vivier Jan 3, 2011
e7592a5
m68k: correctly compute divsl
vivier Jan 14, 2011
da55567
m68k: correctly compute divul
vivier Jan 14, 2011
d152fc8
m68k: add m68030 definition
vivier Jan 15, 2011
ba9f7b8
m68k: FPU rework (draft)
vivier Jan 22, 2011
1eb5c34
m68k: some FPU debugging macros
vivier Jan 24, 2011
bff2576
m68k: more tests
vivier Jan 24, 2011
47f9d31
m68k: correct compute gen_bitfield_cc()
vivier Jan 29, 2011
e3f98c2
m68k: add fgetexp
vivier Feb 14, 2011
858d942
m68k: add fscale
vivier Feb 15, 2011
b7c7f28
m68k: correct addsubq
vivier Feb 25, 2011
2a4d832
m68k: add fetox and flogn
vivier Feb 27, 2011
56816c8
m68k: initialize FRegs, define pickNaN()
vivier Mar 1, 2011
9d9561e
m68k: correct cmpa comparison datatype
vivier Mar 1, 2011
2a59b1c
m68k: add flog10
vivier Mar 2, 2011
7c8ef13
m68k: add cmpm instruction
vivier Mar 3, 2011
a9747d7
m68k: add ftwotox instruction
vivier Mar 5, 2011
1561dac
m68k: better fpu traces
vivier Mar 6, 2011
f7cc50f
m68k: register source operand is always in extended size
vivier Mar 8, 2011
52a6245
m68k: add facos instruction
vivier Mar 9, 2011
df2a9f8
m68k: add ftan instruction
vivier Mar 9, 2011
6566637
m68k: add fsin instruction
vivier Mar 9, 2011
15942c8
m68k: add fcos instruction
vivier Mar 9, 2011
37c36c1
m68k: correct fpcr update
vivier Mar 13, 2011
05ca447
m68k: add fmod instruction
vivier Mar 13, 2011
b4ac350
m68k: flush flags before negx instruction.
vivier Mar 14, 2011
d36dc2c
m68k: correct fmovemx FP registers order.
vivier Mar 15, 2011
0c582df
m68k: add fatan instruction
vivier Mar 15, 2011
8c232b7
m68k: correct bfins instruction
vivier Mar 17, 2011
0039599
m68k: fcmp correctly compares infinity.
vivier Mar 17, 2011
2f1cc98
m68k: allows bfins to manage correctly width = 32
vivier Mar 17, 2011
3ac0ecd
m68k: add ftentox instruction
vivier Mar 17, 2011
aa4955f
m68k: correctly define and manage NaN
vivier Mar 25, 2011
51368e5
m68k: don't call gdb_register_coprocessor() twice.
vivier Mar 21, 2011
ce7aa0c
m68k: gdb FP registers are 96 bits
vivier Mar 23, 2011
2033364
m68k: add exg instruction
vivier Mar 22, 2011
51e8c01
m68k: define floatx80_default_inf_high and floatx80_default_inf_low
vivier Mar 27, 2011
406bdda
m68k: add bkpt instruction
vivier Mar 28, 2011
9be5991
m68k: correctly convert floatx80<->long double
vivier Apr 1, 2011
c91874f
m68k: use expl() to compute exp_FP0()
vivier Apr 1, 2011
4b0d9ac
m68k: use exp2l() to compute exp2_FP0()
vivier Apr 1, 2011
16a6d68
m68k: use logl() to compute ln_FP0()
vivier Apr 1, 2011
a623d65
m68k: use log10l() to compute log10_FP0()
vivier Apr 1, 2011
200c96c
m68k: correctly load signed word into floating point register
vivier Apr 2, 2011
889b437
m68k: add fcosh instruction
vivier Apr 3, 2011
ba0d107
m68k: add fasin instruction
vivier Apr 3, 2011
40f1d35
m68k: add fsincos instruction
vivier Apr 3, 2011
f16e904
m68k: add fsinh instruction
vivier Apr 3, 2011
98274bc
m68k: add ftanh instruction
vivier Apr 3, 2011
02fdf22
m68k: add flognp1 instruction
vivier Apr 3, 2011
f495e4d
m68k: add fatanh instruction
vivier Apr 3, 2011
b58e9f3
Manage NULL QREG in gen_op_load_ea_FP0() and gen_op_store_ea_FP0()
vivier Dec 2, 2012
df87dcd
m68k: compute fpcc and use it in gen_fjmpcc()
vivier Dec 10, 2012
a246806
m68k: add fmove to FPSR
vivier Dec 13, 2012
c9ad2b4
lxc-cross-debian: support of --rootfs parameter
vivier Nov 19, 2013
a9c2308
lxc-cross-debian: remove qemu references
vivier Dec 25, 2013
8ce4565
m68k: correctly manage fmovem post-increment
vivier Jan 17, 2014
322a541
m68k: improve clr
vivier Feb 9, 2014
fe46d47
m68k: improve moveq addsubq
vivier Feb 9, 2014
b00174a
m68k: remove useless (and buggy) SR update from cpu-exec.c
vivier Feb 17, 2014
b09455c
m68k: don't update cc_op twice in branch
vivier Feb 17, 2014
6a59616
m68k: abcd_cc/sbcd_cc need flags in CC_DEST
vivier Mar 14, 2014
f8ca8d7
m68k: rename gen_flush_cc_op() as update_cc_op()
vivier Mar 14, 2014
063d9f0
m68k: don't modify cc_op in helpers
vivier Mar 15, 2014
15e42f2
m68k: flag X is only stored in CC_X, never in CC_DEST
vivier Mar 15, 2014
0c45f76
m68k: no need to flush flags in shift8_reg/shift16_reg/shift_reg
vivier Mar 15, 2014
1aa02c0
m68k: in fbcc, flush flags before jump
vivier Mar 15, 2014
d642797
m68k: discard QREG_CC_SRC when possible
vivier Mar 15, 2014
86500b7
m68k: improve flags management
vivier Mar 16, 2014
ceb65e3
scripts: add a script to create a qemu image disk
vivier Oct 7, 2014
4ec6eff
lxc-img: add a cleanup function
vivier Oct 8, 2014
b929d0a
Revert "qemu/osdep: Remove the need for qemu_init_auxval"
vivier Mar 26, 2015
309cc6f
lxc-fedora: original template
vivier Apr 9, 2015
c5c3a62
lxc-fedora: add interpreter feature
vivier Apr 26, 2015
21b28a7
lxc-fedora: if archs differ, this host can't be in white list
vivier Jun 11, 2015
f8e5e5c
lxc-fedora: manage ppc64le installation
vivier Jun 16, 2015
2802bea
debian-create-lxc: add ppc64le target
vivier Jul 7, 2015
58c710f
lxc-fedora: add interpreter in all bootstrap levels
vivier Jul 16, 2015
cbbbd0e
linux-user,alpha: last available debian sparc release is squeeze
vivier Aug 23, 2015
f81b773
lxc: add s390x
vivier Aug 28, 2015
3b1c6df
lxc: move build to build/ARCH
vivier Aug 29, 2015
17e6671
m68k: fix DEBUG_DISPATCH
vivier Dec 6, 2015
a989825
m68k: re-order cas to manage word size
vivier Dec 9, 2015
0575c62
m68k: CAS/CAS2 cleanup
vivier Dec 5, 2015
79d9d37
m68k: add CAS/CAS2 tests
vivier Dec 6, 2015
1cbf246
m68k: add non-conditionnal entry in the translation array
vivier Dec 8, 2015
d1f48bc
m68k: rework read_imX()
vivier Dec 8, 2015
ca9a979
m68k fix opsize values
vivier Dec 8, 2015
a8a4372
m68k: remove useless pos parameter from insn_opsize()
vivier Dec 8, 2015
78ece7d
m68k: remove useless signed value from SRC_EA() call
vivier Dec 8, 2015
d77b7be
m68k: factorize link/linkl
vivier Dec 8, 2015
96e4d13
m68k: move cmpm to its own function
vivier Dec 8, 2015
a3e3f75
m68k: move exg to its own function
vivier Dec 9, 2015
7f1ade9
target-m68k: Print flags properly
rth7680 Aug 14, 2015
0e4e34c
target-m68k: Some fixes to SR and flags management
rth7680 Aug 14, 2015
9861b31
target-m68k: Remove incorrect clearing of cc_x
rth7680 Aug 14, 2015
4a2cea4
target-m68k: Replace helper_xflag_lt with setcond
rth7680 Aug 14, 2015
657dd4a
Fix do_rt_sigreturn on m68k linux userspace emulation
Dec 12, 2015
34d06aa
m68k: remove useless helper subx8/subx16/addx8/addx16
vivier Dec 11, 2015
f7cfaaf
m68k free some tcg_const_i32()
vivier Dec 13, 2015
bcfc0a7
m68k: rewrite divl to use TCGv_i64
vivier Dec 16, 2015
6dec03a
m68k: rewrite mull to use TCGv_i64
vivier Dec 16, 2015
7b92c57
m68k: rewrite divw
vivier Dec 16, 2015
e7f329d
m68k: rewrite div
vivier Dec 16, 2015
563aa37
m68k: remove useless CC_OP_ADDB, CC_OP_ADDW
vivier Dec 17, 2015
24fba92
m68k: remove useless CC_OP_SUBB, CC_OP_SUBW
vivier Dec 17, 2015
6710812
m68k: remove unused CC_OP_ADDXB, CC_OP_ADDXW, CC_OP_SUBXB, CC_OP_SUBXW
vivier Dec 17, 2015
c7ddf21
m68k: remove unused CC_OP_LOGICB and CC_OP_LOGICW
vivier Dec 17, 2015
6c0e69e
m68k: remove useless CC_OP_SHIFTB and CC_OP_SHIFTW
vivier Dec 17, 2015
8ce86b3
m68k: remove CC_OP_ADDX, CC_OP_SUBX
vivier Dec 18, 2015
5387e9f
target-m68k: Reorg flags handling
vivier Dec 21, 2015
f90983f
m68k: merge flush_flags and get_ccr
vivier Dec 25, 2015
8338af8
target-m68k: Introduce DisasCompare
rth7680 Aug 14, 2015
9605aef
target-m68k: Use setcond for scc
rth7680 Aug 14, 2015
f5472b9
target-m68k: Optimize some comparisons
rth7680 Dec 26, 2015
147ec1e
target-m68k: Optimize gen_flush_flags
rth7680 Aug 14, 2015
ef0137d
target-m68k: Inline immediate shift
vivier Dec 26, 2015
ce3c74f
target-m68k: Inline register shift
vivier Dec 26, 2015
00ef755
target-m68k: Inline memory shift
vivier Dec 26, 2015
4b41439
target-m68k inline subx
vivier Dec 27, 2015
ce316c7
target-m68k inline addx
vivier Dec 27, 2015
d005c82
m68k: replace mul[su]64 helpers by tcg_gen_mul[su]2_i32()
vivier Dec 27, 2015
e1a1393
m68k: replace mul[su]32_cc helpers by tcg_gen_mul[su]2_i32()
vivier Dec 27, 2015
c66e906
m68k: inline divu64/divs64
vivier Dec 27, 2015
8bbcc72
target-m68k: inline divwu/divws
vivier Dec 27, 2015
11f3907
target-m68k: inline divu/divs
vivier Dec 27, 2015
8916613
m68k: rewrite bitfield_load() and bitfield_store()
vivier Apr 17, 2012
351fbe1
target-m68k: replace ror32/rol32 helper by TCG rotr_i32/rotl_i32 op
vivier Dec 28, 2015
8462be6
target-m68k: inline ro[rl][8,16,32]_cc
vivier Dec 28, 2015
478193f
target-m68k: inline rox[rl][8,16,32]_cc
vivier Dec 28, 2015
fea08cc
target-m68k: move FPU helpers to fpu_helper.c
vivier Dec 29, 2015
db9c72b
target-m68k: add missing "move from ccr" for 680x0
vivier Dec 29, 2015
05dfae0
target-m68: rework BCD ops
vivier Dec 29, 2015
ab76276
target-m68k: inline abcd, nbcd, sbcd
vivier Dec 30, 2015
eb9783d
target-m68k: fix addx/negx/subx flags
vivier Dec 31, 2015
90ada32
target-m68k: fix Z flags for ro[x]
vivier Dec 31, 2015
fd8357e
target-m68k: fix eor[bw] flags
vivier Dec 31, 2015
fb8b287
target-m68k: fix or[bw]
vivier Dec 31, 2015
167a9fd
target-m68k: fix sh[lr]
vivier Jan 1, 2016
a66f34a
target-m68k: fix overflow flag for aslb/aslw/asll
vivier Jan 1, 2016
52d96a2
target-m68k: fix divu N/Z flags on overflow
vivier Jan 1, 2016
db5d54a
target-m68: correclty compute V for divs
vivier Jan 2, 2016
6cde31f
target-m68k: fix divul N/Z flags on overflow
vivier Jan 2, 2016
e89c52a
target-m68: correclty compute V for divsl
vivier Jan 2, 2016
bb2fbb3
target - m68k:fix nbcd with invalid digit
vivier Jan 2, 2016
381054c
target-m68k: fix cmp[bw] flags
vivier Jan 2, 2016
6b25774
target-m68k: fix add[bw] flags
vivier Jan 2, 2016
9d968d5
target-m68k: fix sub[bw] flags
vivier Jan 2, 2016
d572597
target-m68k: fix C flags for rol[bwl] and value for rolw
vivier Jan 2, 2016
2ce4453
target-m68k: fix typo
vivier Jan 5, 2016
890fc79
target-m68k: fix roxl[bwl]
vivier Jan 5, 2016
cbcdc0d
target-m68k: fix roxrl
vivier Jan 5, 2016
adcb2d8
target-m68k: Add cc_op state to insn_start
vivier Jan 9, 2016
d0236be
m68k: Build the opcode table only once to avoid multithreading issues
glaubitz Feb 3, 2016
17b4113
m68k: Fix opcode mask for fbcc instruction
glaubitz Feb 3, 2016
3a25eae
m68k: fix use of unitialised temp reg in ASL
trofi Mar 7, 2016
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9 changes: 9 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -109,3 +109,12 @@ cscope.*
tags
TAGS
*~
tests/m68k/fabs
tests/m68k/fdiv
tests/m68k/fmove
tests/m68k/fmovecr
tests/m68k/fmovem
tests/m68k/fmul
tests/m68k/fsub
tests/m68k/fgetexp
tests/m68k/fscale
37 changes: 36 additions & 1 deletion configure
Original file line number Diff line number Diff line change
Expand Up @@ -232,6 +232,7 @@ kvm="no"
rdma=""
gprof="no"
debug_tcg="no"
emulop="no"
debug="no"
fortify_source=""
strip_opt="yes"
Expand Down Expand Up @@ -774,6 +775,10 @@ for opt do
# XXX: backwards compatibility
--enable-trace-backend=*) trace_backends="$optarg"
;;
--*-default-cpu=*)
tmp=`expr "x$opt" : 'x--\(.*\)-default-cpu=.*'`
eval ${tmp}_default_cpu="\"$optarg\""
;;
--with-trace-file=*) trace_file="$optarg"
;;
--enable-gprof) gprof="yes"
Expand Down Expand Up @@ -849,6 +854,10 @@ for opt do
;;
--disable-debug-tcg) debug_tcg="no"
;;
--enable-emulop) emulop="yes"
;;
--disable-emulop) emulop="no"
;;
--enable-debug)
# Enable debugging options that aren't excessively noisy
debug_tcg="yes"
Expand Down Expand Up @@ -1243,6 +1252,7 @@ Standard options:
--target-list=LIST set target list (default: build everything)
$(echo Available targets: $default_target_list | \
fold -s -w 53 | sed -e 's/^/ /')
--ARCH-default-cpu=CPU set the default cpu for a given architecture

Advanced options (experts only):
--source-path=PATH path of source code [$source_path]
Expand Down Expand Up @@ -1364,6 +1374,7 @@ disabled with --disable-FEATURE, default is enabled if available:
numa libnuma support
tcmalloc tcmalloc support
jemalloc jemalloc support
emulop emulation tester helper

NOTE: The object files are built at the place where configure is launched
EOF
Expand Down Expand Up @@ -4684,6 +4695,7 @@ echo "host CPU $cpu"
echo "host big endian $bigendian"
echo "target list $target_list"
echo "tcg debug enabled $debug_tcg"
echo "emulop enabled $emulop"
echo "gprof enabled $gprof"
echo "sparse enabled $sparse"
echo "strip binaries $strip_opt"
Expand Down Expand Up @@ -5460,6 +5472,7 @@ target_dir="$target"
config_target_mak=$target_dir/config-target.mak
target_name=`echo $target | cut -d '-' -f 1`
target_bigendian="no"
target_default_cpu="\"any\""

case "$target_name" in
armeb|lm32|m68k|microblaze|mips|mipsn32|mips64|moxie|or32|ppc|ppcemb|ppc64|ppc64abi32|s390x|sh4eb|sparc|sparc64|sparc32plus|xtensaeb)
Expand Down Expand Up @@ -5507,9 +5520,11 @@ TARGET_ABI_DIR=""

case "$target_name" in
i386)
target_default_cpu="\"qemu32\""
;;
x86_64)
TARGET_BASE_ARCH=i386
target_default_cpu="\"qemu64\""
;;
alpha)
;;
Expand All @@ -5529,7 +5544,7 @@ case "$target_name" in
;;
m68k)
bflt="yes"
gdb_xml_files="cf-core.xml cf-fp.xml"
gdb_xml_files="cf-core.xml cf-fp.xml m68k-fp.xml"
;;
microblaze|microblazeel)
TARGET_ARCH=microblaze
Expand All @@ -5538,17 +5553,20 @@ case "$target_name" in
mips|mipsel)
TARGET_ARCH=mips
echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak
target_default_cpu="\"24Kf\""
;;
mipsn32|mipsn32el)
TARGET_ARCH=mips64
TARGET_BASE_ARCH=mips
echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak
echo "TARGET_ABI32=y" >> $config_target_mak
target_default_cpu="\"5KEf\""
;;
mips64|mips64el)
TARGET_ARCH=mips64
TARGET_BASE_ARCH=mips
echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak
target_default_cpu="\"5KEf\""
;;
moxie)
;;
Expand All @@ -5558,44 +5576,53 @@ case "$target_name" in
;;
ppc)
gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
target_default_cpu="\"750\""
;;
ppcemb)
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml power-spe.xml"
target_default_cpu="\"750\""
;;
ppc64)
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
target_default_cpu="\"POWER8\""
;;
ppc64le)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
target_default_cpu="\"POWER8\""
;;
ppc64abi32)
TARGET_ARCH=ppc64
TARGET_BASE_ARCH=ppc
TARGET_ABI_DIR=ppc
echo "TARGET_ABI32=y" >> $config_target_mak
gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml"
target_default_cpu="\"750\""
;;
sh4|sh4eb)
TARGET_ARCH=sh4
bflt="yes"
target_default_cpu=TYPE_SH7785_CPU
;;
sparc)
target_default_cpu="\"Fujitsu MB86904\""
;;
sparc64)
TARGET_BASE_ARCH=sparc
target_default_cpu="\"TI UltraSparc II\""
;;
sparc32plus)
TARGET_ARCH=sparc64
TARGET_BASE_ARCH=sparc
TARGET_ABI_DIR=sparc
echo "TARGET_ABI32=y" >> $config_target_mak
target_default_cpu="\"TI UltraSparc II\""
;;
s390x)
gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml s390-cr.xml s390-virt.xml"
Expand Down Expand Up @@ -5624,6 +5651,11 @@ upper() {
echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]'
}

tmp_target_default_cpu=`eval echo \\$${target_name}_default_cpu`
if [ "x$tmp_target_default_cpu" != "x" ] ; then
target_default_cpu="\"$tmp_target_default_cpu\""
fi
echo "TARGET_DEFAULT_CPU=$target_default_cpu" >> $config_target_mak
target_arch_name="`upper $TARGET_ARCH`"
echo "TARGET_$target_arch_name=y" >> $config_target_mak
echo "TARGET_NAME=$target_name" >> $config_target_mak
Expand Down Expand Up @@ -5688,6 +5720,9 @@ if test ! -z "$gdb_xml_files" ; then
echo "TARGET_XML_FILES=$list" >> $config_target_mak
fi

if test "$target_user_only" = "yes" -a "$target_name" = "m68k" -a "$emulop" = "yes" ; then
echo "CONFIG_EMULOP=y" >> $config_target_mak
fi
if test "$target_user_only" = "yes" -a "$bflt" = "yes"; then
echo "TARGET_HAS_BFLT=y" >> $config_target_mak
fi
Expand Down
6 changes: 0 additions & 6 deletions cpu-exec.c
Original file line number Diff line number Diff line change
Expand Up @@ -142,12 +142,6 @@ static inline tcg_target_ulong cpu_tb_exec(CPUState *cpu, uint8_t *tb_ptr)
if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
#if defined(TARGET_I386)
log_cpu_state(cpu, CPU_DUMP_CCOP);
#elif defined(TARGET_M68K)
/* ??? Should not modify env state for dumping. */
cpu_m68k_flush_flags(env, env->cc_op);
env->cc_op = CC_OP_FLAGS;
env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4);
log_cpu_state(cpu, 0);
#else
log_cpu_state(cpu, 0);
#endif
Expand Down
48 changes: 44 additions & 4 deletions fpu/softfloat-specialize.h
Original file line number Diff line number Diff line change
Expand Up @@ -113,7 +113,7 @@ const float16 float16_default_nan = const_float16(0xFE00);
#if defined(TARGET_SPARC)
const float32 float32_default_nan = const_float32(0x7FFFFFFF);
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_XTENSA) || defined(TARGET_S390X)
defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_M68K)
const float32 float32_default_nan = const_float32(0x7FC00000);
#elif SNAN_BIT_IS_ONE
const float32 float32_default_nan = const_float32(0x7FBFFFFF);
Expand All @@ -127,7 +127,7 @@ const float32 float32_default_nan = const_float32(0xFFC00000);
#if defined(TARGET_SPARC)
const float64 float64_default_nan = const_float64(LIT64( 0x7FFFFFFFFFFFFFFF ));
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_S390X)
defined(TARGET_S390X) || defined(TARGET_M68K)
const float64 float64_default_nan = const_float64(LIT64( 0x7FF8000000000000 ));
#elif SNAN_BIT_IS_ONE
const float64 float64_default_nan = const_float64(LIT64(0x7FF7FFFFFFFFFFFF));
Expand All @@ -138,7 +138,10 @@ const float64 float64_default_nan = const_float64(LIT64( 0xFFF8000000000000 ));
/*----------------------------------------------------------------------------
| The pattern for a default generated extended double-precision NaN.
*----------------------------------------------------------------------------*/
#if SNAN_BIT_IS_ONE
#if defined(TARGET_M68K)
#define floatx80_default_nan_high 0x7FFF
#define floatx80_default_nan_low LIT64( 0x4000000000000000 )
#elif SNAN_BIT_IS_ONE
#define floatx80_default_nan_high 0x7FFF
#define floatx80_default_nan_low LIT64(0xBFFFFFFFFFFFFFFF)
#else
Expand All @@ -149,6 +152,21 @@ const float64 float64_default_nan = const_float64(LIT64( 0xFFF8000000000000 ));
const floatx80 floatx80_default_nan
= make_floatx80_init(floatx80_default_nan_high, floatx80_default_nan_low);

/*----------------------------------------------------------------------------
| The pattern for a default generated extended double-precision inf.
*----------------------------------------------------------------------------*/

#if defined(TARGET_M68K)
#define floatx80_default_inf_high 0x7FFF
#define floatx80_default_inf_low LIT64( 0x0000000000000000 )
#else
#define floatx80_default_inf_high 0x7FFF
#define floatx80_default_inf_low LIT64( 0x8000000000000000 )
#endif

const floatx80 floatx80_default_inf
= make_floatx80_init(floatx80_default_inf_high, floatx80_default_inf_low);

/*----------------------------------------------------------------------------
| The pattern for a default generated quadruple-precision NaN. The `high' and
| `low' values hold the most- and least-significant bits, respectively.
Expand Down Expand Up @@ -475,6 +493,26 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
return 1;
}
}
#elif defined(TARGET_M68K)
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
{
/* If either operand, but not both operands, of an operation is a
* nonsignaling NAN, then that NAN is returned as the result. If both
* operands are nonsignaling NANs, then the destination operand
* nonsignaling NAN is returned as the result.
*/

if (aIsSNaN) {
return 0;
} else if (bIsSNaN) {
return 1;
} else if (bIsQNaN) {
return 1;
} else {
return 0;
}
}
#else
static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN,
flag aIsLargerSignificand)
Expand Down Expand Up @@ -974,7 +1012,9 @@ int floatx80_is_signaling_nan( floatx80 a )
floatx80 floatx80_maybe_silence_nan( floatx80 a )
{
if (floatx80_is_signaling_nan(a)) {
#if SNAN_BIT_IS_ONE
#if defined(TARGET_M68K)
a.low |= LIT64( 0x4000000000000000 );
#elif SNAN_BIT_IS_ONE
# if defined(TARGET_MIPS) || defined(TARGET_SH4) || defined(TARGET_UNICORE32)
a.low = floatx80_default_nan_low;
a.high = floatx80_default_nan_high;
Expand Down
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