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VLSI Design & Automation Group

UC Santa Cruz VLSI Design and Automation research lab

101 followers
Santa Cruz, CA
http://vlsida.github.io
mrg+vlsida@ucsc.edu

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OpenRAM OpenRAM Public

An open-source static random access memory (SRAM) compiler.

Python 750 190
openram-docker-image openram-docker-image Public

Shell 5 2
openram-vagrant-image openram-vagrant-image Public

Settings to build a Vagrant image for OpenRAM

Shell 4 2

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All C C++ Dockerfile Python Ruby Shell SourcePawn Verilog

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Showing 10 of 27 repositories

openram_testchip Public Forked from efabless/caravel_user_project
https://caravel-user-project.readthedocs.io

Verilog 9 Apache-2.0 324 0 1 Updated Apr 16, 2024
OpenRAM Public
An open-source static random access memory (SRAM) compiler.

Python 750 BSD-3-Clause 190 33 (2 issues need help) 9 Updated Mar 26, 2024
OpenCache Public
An open-source custom cache generator.

Python 24 BSD-3-Clause 3 0 0 Updated Mar 14, 2024
vlsida-eda Public
Conda recipes for VLSIDA projects.

Shell 4 BSD-3-Clause 0 0 0 Updated Dec 20, 2023
sky130_fd_bd_sram Public

0 Apache-2.0 0 0 0 Updated Nov 1, 2023
openram_testchip2 Public

Verilog 2 Apache-2.0 0 0 0 Updated Sep 12, 2023
sky130_sram_macros Public

SourcePawn 5 Apache-2.0 7 0 0 Updated Sep 8, 2023
OpenROAD Public Forked from The-OpenROAD-Project/OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow

Verilog 4 BSD-3-Clause 485 0 0 Updated Jun 6, 2023
OpenLane Public Forked from The-OpenROAD-Project/OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

SourcePawn 1 Apache-2.0 355 0 0 Updated Jun 6, 2023
sky130_klayout_pdk Public Forked from mabrains/sky130_klayout_pdk
Skywater 130nm Klayout Device Generators PDK

Python 1 AGPL-3.0 12 0 0 Updated Apr 27, 2023

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