Verilog vs liberty output mismatch #44

tetra12 · 2018-12-12T17:39:06Z

Issue: Bug
Severity: High
Description: When I generate a default SRAM from your example for the latest gscl45 with -n option, the output verilog has OEb pin, which is NOT available in the liberty output. This results in a synthesis fail when I synthesize a wrapper for the generated memory. Pls fix this

mguthaus · 2018-12-12T17:46:00Z

Thanks, we are aware of this issue and it will be fixed in an upcoming release very soon.

We have separated the data bus into separate din and dout ports so the OEb is no longer necessary but was not removed from the verilog.

tetra12 · 2018-12-12T19:30:03Z

Excellent, thank you! So I'll simply remove this OEb port from my verilog.

Another issue is related. Yosys fails to parse the liberty output in current format:
pin(DOUT0[63:0]){ ... }

My workaround is to remove brackets [63:0] and leave pin (DOUT0) {...}. Please remove this from your scripts as well

tetra12 · 2018-12-16T12:01:34Z

Thank you. Waiting forward working with your next release. Any contributions required ?

mguthaus · 2018-12-16T12:28:35Z

This will not be in an update release until after the new year. If there are suggestions about how to fix the lib file for yosys, that would be useful. The current one generally works in other static timing tools but we will have some updates to the edge relations in the new release. Matt

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On Sun, Dec 16, 2018, 09:01 tetra12 ***@***.*** wrote: Thank you. Waiting forward working with your next release. Any contributions required ? — You are receiving this because you commented. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L3EAX2qgMtx4K-HyZou8TKFUMR_lks5u5jYfgaJpZM4ZQHtc> .

tetra12 · 2018-12-16T19:43:22Z

@mguthaus Yosys parses the *.lib files if you remove bus widths from pin descriptions :
pin(DOUT0[63:0]){ ... } -> pin(DOUT0){ ... }

I also made a verilog wrapper for your memories to match lib files. I was able to synthesize it with an updated lib file in Yosys.

mguthaus · 2018-12-16T19:56:37Z

But won't that break most other static timers (Primetime, OpenSTA)? They need to recognize each bus pin...

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On Sun, Dec 16, 2018, 16:43 tetra12 ***@***.*** wrote: @mguthaus <https://github.com/mguthaus> Yosys parses the *.lib files if you remove bus widths from pin descriptions : pin(DOUT0[63:0]){ ... } -> pin(DOUT0){ ... } I also made a verilog wrapper for your memories to match lib files. I was able to synthesize it with an updated lib file in Yosys. — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L3FJ9XG39a73h7ld1x7svonoegbPks5u5qJagaJpZM4ZQHtc> .

mguthaus · 2018-12-16T19:57:26Z

Maybe this is a bug in how yosys parses .lib files...

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--- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

On Sun, Dec 16, 2018, 16:56 Matthew Guthaus ***@***.*** wrote: But won't that break most other static timers (Primetime, OpenSTA)? They need to recognize each bus pin... On Sun, Dec 16, 2018, 16:43 tetra12 ***@***.*** wrote: > @mguthaus <https://github.com/mguthaus> Yosys parses the *.lib files if > you remove bus widths from pin descriptions : > pin(DOUT0[63:0]){ ... } -> pin(DOUT0){ ... } > > I also made a verilog wrapper for your memories to match lib files. I was > able to synthesize it with an updated lib file in Yosys. > > — > You are receiving this because you were mentioned. > Reply to this email directly, view it on GitHub > <#44 (comment)>, or mute > the thread > <https://github.com/notifications/unsubscribe-auth/AL35L3FJ9XG39a73h7ld1x7svonoegbPks5u5qJagaJpZM4ZQHtc> > . >

tetra12 · 2018-12-16T20:19:34Z

Pls leave your comment here too: https://www.reddit.com/r/yosys/comments/a4ovm6/liberty_syntax_support/

I'm working with Tim now. No problems in qflow with that. I don't have access to commercial tools, so pls check on your own or give me access to your tools for test purposes.

tetra12 · 2018-12-17T14:17:04Z

I confirm that updated *.lib file works seamlessly with opensta. Synthesized, checked.
Please, follow my feedback and remove bus width in the next release.

Here's my wrapper for your SRAM. Feel free to update your verilog output as well

Thank you!

mguthaus · 2018-12-17T17:28:36Z

Did you confirm the timing was right or that it just read it in?

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--- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

On Mon, Dec 17, 2018, 11:17 tetra12 ***@***.*** wrote: I confirm that updated *.lib file works seamlessly with opensta. Synthesized, checked. Please, follow my feedback and remove bus width in the next release. Here's my wrapper <https://drive.google.com/open?id=1mAVa5DuBOb1eI0WkYoxfaQSkNo12Woc0> for your SRAM. Feel free to update your verilog output as well Thank you! — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L26v-OhJt9u3zSByhJCG9k_QQNTPks5u56dhgaJpZM4ZQHtc> .

mguthaus · 2018-12-17T17:37:29Z

My guess is that the will make adding timing constraints problematic. These need to use indexed buses like DOUT0[1] so removing the indices may prevent that. Even if it does "work" does it then count all of the bits as the same timing point? That would not be correct either. I think we should instead fix Yosys.

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On Mon, Dec 17, 2018, 14:28 Matthew Guthaus ***@***.*** wrote: Did you confirm the timing was right or that it just read it in? --- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg On Mon, Dec 17, 2018, 11:17 tetra12 ***@***.*** wrote: > I confirm that updated *.lib file works seamlessly with opensta. > Synthesized, checked. > Please, follow my feedback and remove bus width in the next release. > > Here's my wrapper > <https://drive.google.com/open?id=1mAVa5DuBOb1eI0WkYoxfaQSkNo12Woc0> for > your SRAM. Feel free to update your verilog output as well > > Thank you! > > — > You are receiving this because you were mentioned. > Reply to this email directly, view it on GitHub > <#44 (comment)>, or mute > the thread > <https://github.com/notifications/unsubscribe-auth/AL35L26v-OhJt9u3zSByhJCG9k_QQNTPks5u56dhgaJpZM4ZQHtc> > . >

tetra12 · 2018-12-17T18:11:37Z

I synthesized your SRAM with my verilog wrapper and run the opensta script to obtain timing report. I used OSU035 with a 10ns clock, which yielded in a 9.86ns slack. Do you want to get my scripts ?

tetra12 · 2018-12-17T18:13:22Z

If you think it is the Yosys issue, pls feel free to open a RFC for this in the Yosys repo. If you want to double check my scripts, let me know. I'll share

mguthaus · 2018-12-17T18:15:25Z

Yes, please share your scripts.

…

--- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

On Mon, Dec 17, 2018, 15:13 tetra12 ***@***.*** wrote: If you think it is the Yosys issue, pls feel free to open a RFC for this in the Yosys repo. If you want to double check my scripts, let me know. I'll share — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L4sO59CTBHdOxpQ0W_BoF7oGwYTTks5u597CgaJpZM4ZQHtc> .

tetra12 · 2018-12-17T18:25:23Z

Pls check here

tetra12 · 2018-12-18T09:24:30Z

Any follow up questions? Should I close this issue ?

mguthaus · 2018-12-18T09:48:55Z

I'm on vacation right now, so no... We will look at this for the next release.

…

--- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

On Tue, Dec 18, 2018, 06:24 tetra12 ***@***.*** wrote: Any follow up questions? Should I close this issue ? — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35Lz06ROs77IdiTLLZHkYcAArj4H9Iks5u6LRPgaJpZM4ZQHtc> .

tetra12 · 2019-01-04T18:48:19Z

Happy New Year! Any news?

mguthaus · 2019-01-04T18:56:53Z

Not yet, unfortunately class prep must take priority.

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On Fri, Jan 4, 2019 at 10:48 AM tetra12 ***@***.***> wrote: Happy New Year! Any news? — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L5KhNqKceRBedgLog8oGtCc1ECsBks5u_6H0gaJpZM4ZQHtc> .

-- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

mguthaus · 2019-01-09T20:18:23Z

I've confirmed that your suggested change to the lib file works in all timing analyzers that I can use. So, I have added it to our private repository and it will be in the next OpenRAM release -- probably by the end of this week. Thanks for your patience. On Fri, Jan 4, 2019 at 10:56 AM Matt Guthaus <notifications@github.com> wrote:

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Not yet, unfortunately class prep must take priority. On Fri, Jan 4, 2019 at 10:48 AM tetra12 ***@***.***> wrote: > Happy New Year! Any news? > > — > You are receiving this because you were mentioned. > Reply to this email directly, view it on GitHub > <#44 (comment)>, or mute > the thread > < https://github.com/notifications/unsubscribe-auth/AL35L5KhNqKceRBedgLog8oGtCc1ECsBks5u_6H0gaJpZM4ZQHtc > > . > -- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35Lyje8iZG2FhiDkDucWwWYzZ0eszmks5u_6P1gaJpZM4ZQHtc> .

-- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

tetra12 · 2019-01-10T13:57:52Z

Sounds great. Let me know if I can contribute in this project. I can do testing, validation, integration and verification, since I use your stuff in my commercial project.

If you have an idea, let me know

mguthaus · 2019-01-10T18:04:40Z

Can you send me an email outside of GitHub at mrg@ucsc.edu. I'm interested in learning more and seeing how we can collaborate. Matt

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On Thu, Jan 10, 2019 at 5:57 AM tetra12 ***@***.***> wrote: Sounds great. Let me know if I can contribute in this project. I can do testing, validation, integration and verification, since I use your stuff in my commercial project. If you have an idea, let me know — You are receiving this because you were mentioned. Reply to this email directly, view it on GitHub <#44 (comment)>, or mute the thread <https://github.com/notifications/unsubscribe-auth/AL35L2zQQMBP_bo6X_RH9rZQpxfKnLKiks5vB0bggaJpZM4ZQHtc> .

-- Matthew Guthaus Professor, Computer Science and Engineering University of California Santa Cruz https://www.soe.ucsc.edu/people/mrg

mguthaus · 2019-02-22T23:40:14Z

I finally got to trying this out in Library Compiler and it fails without these bus notations.

Reading '/home/mrg/OpenRAMLibrary/deliverables/freepdk45/2019-02-21/sram_8b_512_1rw_freepdk45/sram_8b_512_1rw_freepdk45_TT_1p0V_25C.lib' ...
Error: Line 96, Cell 'sram_8b_512_1rw_freepdk45', bus 'DIN0', Invalid bus syntax is detected in 'DIN0'. (LBDB-176)
Error: Line 135, Cell 'sram_8b_512_1rw_freepdk45', bus 'DOUT0', Invalid bus syntax is detected in 'DOUT0'. (LBDB-176)
Error: Line 169, Cell 'sram_8b_512_1rw_freepdk45', bus 'ADDR0', Invalid bus syntax is detected in 'ADDR0'. (LBDB-176)

Unfortunately, I will need to add them back and we should fix Yosys.

mguthaus · 2019-02-23T00:35:11Z

This issue was coincidentally opened 4 hours ago for Yosys:
YosysHQ/yosys#825

tetra12 closed this as completed Jan 11, 2019

mguthaus reopened this Feb 22, 2019

mguthaus closed this as completed Aug 29, 2019

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Verilog vs liberty output mismatch #44

Verilog vs liberty output mismatch #44

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Verilog vs liberty output mismatch #44

Verilog vs liberty output mismatch #44

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