Added alu and test.

src/alu.v

@@ -0,0 +1,23 @@
+/**
+ * Arithmetic Logic Unit.
+ */
+module alu
+  (
+   input [2:0]       ctrl,
+   input [31:0]      src_a, src_b,
+   output reg [31:0] result);
+
+   always @(*) begin
+      case (ctrl)
+        0: result = src_a & src_b;
+        1: result = src_a | src_b;
+        2: result = src_a + src_b;
+        4: result = src_a & ~src_b;
+        5: result = src_a | ~src_b;
+        6: result = src_a - src_b;
+        7: result = src_a < src_b;
+        default: result = src_a + src_b;
+      endcase // case (ctrl)
+   end // always begin
+endmodule // alu
+

test/test_alu.v

@@ -0,0 +1,45 @@
+/**
+ * Test - Arithmetic Logic Unit.
+ * Basic sanity check to make sure the language is understood.
+ */
+module test_alu();
+
+   reg [2:0]   ctrl;
+   reg [31:0]  src_a, src_b;
+   wire [31:0] result;
+
+
+   // Instantiate the device-under-test (dut).
+   alu dut(ctrl, src_a, src_b, result);
+
+   // Apply test inputs one at a time and verify outputs.
+   initial begin
+      $display("Starting Test.");
+
+      // Read the first instruction.
+      ctrl = 0; src_a = 'hF0F0; src_b = 'hF00F; #10;
+      if (result !== 'hF000) $display("AND operation failed:  %h", result);
+
+      ctrl = 1; #10;
+      if (result !== 'hF0FF) $display("OR operation failed:  %h", result);
+
+      ctrl = 2; #10;
+      if (result !== 'h1E0FF) $display("ADD operation failed:  %h", result);
+
+      ctrl = 6; #10;
+      if (result !== 'hE1) $display("SUB operation failed:  %h", result);
+
+      ctrl = 7; #10;
+      if (result !== 0) $display("SLT greater than test failed:  %h", result);
+
+      src_a = 'hF00F; src_b = 'hF0F0; #10;
+      if (result !== 1) $display("SLT less than test failed:  %h", result);
+
+      src_a = 'hF00F; src_b = 'hF00F; #10;
+      if (result !== 0) $display("SLT equal test failed:  %h", result);
+
+      $display("Test Complete.");
+
+   end // initial begin
+endmodule // test_imem
+