fixes

drivers/gpu/drm/drm_atomic.c

@@ -1183,14 +1183,13 @@ static int drm_atomic_connector_set_property(struct drm_connector *connector,
 		 */
 		if (state->link_status != DRM_LINK_STATUS_GOOD)
 			state->link_status = val;
-		} else if (property == config->hdr_source_metadata_property) {
-			ret = drm_atomic_replace_property_blob_from_id(dev,
-					&state->hdr_source_metadata_blob_ptr,
-					val,
-					-1,
-					&replaced);
-			state->hdr_metadata_changed |= replaced;
-			return ret;
+	} else if (property == config->hdr_source_metadata_property) {
+		ret = drm_atomic_replace_property_blob_from_id(dev,
+							       &state->hdr_source_metadata_blob_ptr,
+							       val,
+							       -1,
+							       &replaced);
+		return ret;
 	} else if (property == config->aspect_ratio_property) {
 		state->picture_aspect_ratio = val;
 	} else if (property == connector->scaling_mode_property) {

drivers/gpu/drm/drm_edid.c

@@ -2816,16 +2816,6 @@ add_detailed_modes(struct drm_connector *connector, struct edid *edid,
 #define COLORIMETRY_DATA_BLOCK		0x5
 #define HDR_STATIC_METADATA_BLOCK	0x6
 
-/* HDR Metadata Block: Bit fields */
-#define SUPPORTED_EOTF_MASK            0x3f
-#define TRADITIONAL_GAMMA_SDR          (0x1 << 0)
-#define TRADITIONAL_GAMMA_HDR          (0x1 << 1)
-#define SMPTE_ST2084                   (0x1 << 2)
-#define FUTURE_EOTF                    (0x1 << 3)
-#define RESERVED_EOTF                  (0x3 << 4)
-
-#define STATIC_METADATA_TYPE1          (0x1 << 0)
-
 /*
  * Search EDID for CEA extension block.
  */
@@ -3810,26 +3800,16 @@ static bool cea_db_is_hdmi_hdr_metadata_block(const u8 *db)
 
 static uint16_t eotf_supported(const u8 *edid_ext)
 {
-	uint16_t val = 0;
-
-	if (edid_ext[2] & TRADITIONAL_GAMMA_SDR)
-		val |= TRADITIONAL_GAMMA_SDR;
-	if (edid_ext[2] & TRADITIONAL_GAMMA_HDR)
-		val |= TRADITIONAL_GAMMA_HDR;
-	if (edid_ext[2] & SMPTE_ST2084)
-		val |= SMPTE_ST2084;
-
-	return val;
+	return edid_ext[2] &
+		(BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) |
+		 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) |
+		 BIT(HDMI_EOTF_SMPTE_ST2084));
 }
 
 static uint16_t hdr_metadata_type(const u8 *edid_ext)
 {
-	uint16_t val = 0;
-
-	if (edid_ext[3] & STATIC_METADATA_TYPE1)
-		val |= STATIC_METADATA_TYPE1;
-
-	return val;
+	return edid_ext[3] &
+		BIT(HDMI_STATIC_METADATA_TYPE1);
 }
 
 static void
@@ -3840,18 +3820,15 @@ drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db)
 	return;
 
 	len = cea_db_payload_len(db);
-	connector->hdr_panel_metadata->eotf = eotf_supported(db);
-	connector->hdr_panel_metadata->type = hdr_metadata_type(db);
+	connector->hdr_metadata.eotf = eotf_supported(db);
+	connector->hdr_metadata.metadata_type = hdr_metadata_type(db);
 
-	if (len == 6) {
-		connector->hdr_panel_metadata->max_cll = db[4];
-		connector->hdr_panel_metadata->max_fall = db[5];
-		connector->hdr_panel_metadata->min_cll = db[6];
-	} else if (len == 5) {
-		connector->hdr_panel_metadata->max_cll = db[4];
-		connector->hdr_panel_metadata->max_fall = db[5];
-	} else if (len == 4)
-		connector->hdr_panel_metadata->max_cll = db[4];
+	if (len >= 6)
+		;//connector->hdr_metadata.min_cll = db[6];
+	if (len >= 5)
+		connector->hdr_metadata.max_fall = db[5];
+	if (len >= 4)
+		connector->hdr_metadata.max_cll = db[4];
 
 }
 
@@ -4891,23 +4868,24 @@ drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
 	if (err < 0)
 		return err;
 
+	DRM_DEBUG_KMS("type = %x\n", frame->type);
+
 	hdr_source_metadata = (struct hdr_static_metadata *)hdr_metadata;
 
 	frame->length = sizeof(struct hdr_static_metadata);
 
-
 	frame->eotf = hdr_source_metadata->eotf;
-	frame->type = hdr_source_metadata->type;
+	frame->metadata_type = hdr_source_metadata->metadata_type;
 
 	for (i = 0; i < 3; i++) {
-		frame->display_primaries_x[i] =
-			hdr_source_metadata->display_primaries_x[i];
-		frame->display_primaries_y[i] =
-			hdr_source_metadata->display_primaries_y[i];
+		frame->display_primaries[i].x =
+			hdr_source_metadata->display_primaries[i].x;
+		frame->display_primaries[i].y =
+			hdr_source_metadata->display_primaries[i].y;
 	}
 
-	frame->white_point_x = hdr_source_metadata->white_point_x;
-	frame->white_point_y = hdr_source_metadata->white_point_y;
+	frame->white_point.x = hdr_source_metadata->white_point.x;
+	frame->white_point.y = hdr_source_metadata->white_point.y;
 
 	frame->max_mastering_display_luminance =
 		hdr_source_metadata->max_mastering_display_luminance;
@@ -4917,6 +4895,10 @@ drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame,
 	frame->max_cll = hdr_source_metadata->max_cll;
 	frame->max_fall = hdr_source_metadata->max_fall;
 
+	DRM_DEBUG_KMS("sika\n");
+	hdmi_infoframe_log(KERN_CRIT, NULL,
+			   (union hdmi_infoframe*)frame);
+	DRM_DEBUG_KMS("sika 2\n");
 	return 0;
 }
 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata);
@@ -5007,6 +4989,10 @@ drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame,
 				   bool rgb_quant_range_selectable,
 				   bool is_hdmi2_sink)
 {
+	DRM_DEBUG_KMS("quant %d %d qs=%d\n",
+		      rgb_quant_range, drm_default_rgb_quant_range(mode),
+		      rgb_quant_range_selectable);
+
 	/*
 	 * CEA-861:
 	 * "A Source shall not send a non-zero Q value that does not correspond

drivers/gpu/drm/i915/i915_reg.h

@@ -4089,12 +4089,21 @@ enum {
 #define   EDP_PSR_PERF_CNT_MASK		0xffffff
 
 #define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
-#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
-#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
-#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
-#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)
-#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE    (1<<16)
-#define   EDP_PSR_DEBUG_EXIT_ON_PIXEL_UNDERRUN (1<<15)
+#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP           (1<<28)
+#define   EDP_PSR_DEBUG_MASK_LPSP                (1<<27)
+#define   EDP_PSR_DEBUG_MASK_MEMUP               (1<<26)
+#define   EDP_PSR_DEBUG_MASK_HPD                 (1<<25)
+#define   EDP_PSR_DEBUG_MASK_FBC_MODIFY          (1<<24)
+#define   EDP_PSR_DEBUG_MASK_FLIP_PENDING        (1<<23)
+#define   EDP_PSR_DEBUG_MASK_HDCP_ENABLE         (1<<22)
+#define   EDP_PSR_DEBUG_MASK_SPRITE_ENABLE       (1<<21)
+#define   EDP_PSR_DEBUG_MASK_CURSOR_MOVE         (1<<20)
+#define   EDP_PSR_DEBUG_MASK_VBLANK_VSYNC_INT_EN (1<<19)
+#define   EDP_PSR_DEBUG_MASK_DPST_PHASEIN_EN     (1<<18)
+#define   EDP_PSR_DEBUG_MASK_KVMR_SESSION_EN     (1<<17)
+#define   EDP_PSR_DEBUG_MASK_DISP_REG_WRITE      (1<<16)
+#define   EDP_PSR_DEBUG_ENTRY_COMPLETION         (1<<1)
+#define   EDP_PSR_DEBUG_REDUCE_COUNT             (1<<0)
 
 #define EDP_PSR2_CTL			_MMIO(0x6f900)
 #define   EDP_PSR2_ENABLE		(1<<31)
@@ -4448,6 +4457,7 @@ enum {
 #define   VIDEO_DIP_FREQ_2VSYNC		(2 << 16)
 #define   VIDEO_DIP_FREQ_MASK		(3 << 16)
 /* HSW and later: */
+#define   VIDEO_DIP_ENABLE_DRM_GLK	(1 << 28)
 #define   VIDEO_DIP_ENABLE_VSC_HSW	(1 << 20)
 #define   VIDEO_DIP_ENABLE_GCP_HSW	(1 << 16)
 #define   VIDEO_DIP_ENABLE_AVI_HSW	(1 << 12)
@@ -7431,6 +7441,8 @@ enum {
 #define _HSW_VIDEO_DIP_SPD_DATA_A	0x602A0
 #define _HSW_VIDEO_DIP_GMP_DATA_A	0x602E0
 #define _HSW_VIDEO_DIP_VSC_DATA_A	0x60320
+#define _GLK_VIDEO_DIP_DRM_DATA_A	0x60440
+
 #define _HSW_VIDEO_DIP_AVI_ECC_A	0x60240
 #define _HSW_VIDEO_DIP_VS_ECC_A		0x60280
 #define _HSW_VIDEO_DIP_SPD_ECC_A	0x602C0
@@ -7444,6 +7456,8 @@ enum {
 #define _HSW_VIDEO_DIP_SPD_DATA_B	0x612A0
 #define _HSW_VIDEO_DIP_GMP_DATA_B	0x612E0
 #define _HSW_VIDEO_DIP_VSC_DATA_B	0x61320
+#define _GLK_VIDEO_DIP_DRM_DATA_B	0x61440
+
 #define _HSW_VIDEO_DIP_BVI_ECC_B	0x61240
 #define _HSW_VIDEO_DIP_VS_ECC_B		0x61280
 #define _HSW_VIDEO_DIP_SPD_ECC_B	0x612C0
@@ -7457,6 +7471,7 @@ enum {
 #define HSW_TVIDEO_DIP_SPD_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4)
 #define HSW_TVIDEO_DIP_GCP(trans)		_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A)
 #define HSW_TVIDEO_DIP_VSC_DATA(trans, i)	_MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4)
+#define GLK_TVIDEO_DIP_DRM_DATA(trans, i)	_MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4)
 
 #define _HSW_STEREO_3D_CTL_A		0x70020
 #define   S3D_ENABLE			(1<<31)

drivers/gpu/drm/i915/intel_atomic.c

@@ -99,6 +99,16 @@ int intel_digital_connector_atomic_set_property(struct drm_connector *connector,
 	return -EINVAL;
 }
 
+static bool blob_equal(const struct drm_property_blob *a,
+		       const struct drm_property_blob *b)
+{
+	if (a && b)
+		return a->length == b->length &&
+			!memcmp(a->data, b->data, a->length);
+
+	return !a == !b;
+}
+
 int intel_digital_connector_atomic_check(struct drm_connector *conn,
 					 struct drm_connector_state *new_state)
 {
@@ -122,7 +132,9 @@ int intel_digital_connector_atomic_check(struct drm_connector *conn,
 	if (new_conn_state->force_audio != old_conn_state->force_audio ||
 	    new_conn_state->broadcast_rgb != old_conn_state->broadcast_rgb ||
 	    new_conn_state->base.picture_aspect_ratio != old_conn_state->base.picture_aspect_ratio ||
-	    new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode)
+	    new_conn_state->base.scaling_mode != old_conn_state->base.scaling_mode ||
+	    !blob_equal(new_conn_state->base.hdr_source_metadata_blob_ptr,
+			old_conn_state->base.hdr_source_metadata_blob_ptr))
 		crtc_state->mode_changed = true;
 
 	return 0;

drivers/gpu/drm/i915/intel_color.c

@@ -622,23 +622,31 @@ int intel_color_check(struct drm_crtc *crtc,
 		sizeof(struct drm_color_lut);
 
 	/*
-	 * We allow both degamma & gamma luts at the right size or
-	 * NULL.
+	 * We allow no degamma lut/ctm and a gamma lut at the legacy
+	 * size (256 entries).
 	 */
-	if ((!crtc_state->degamma_lut ||
-	     crtc_state->degamma_lut->length == degamma_length) &&
-	    (!crtc_state->gamma_lut ||
-	     crtc_state->gamma_lut->length == gamma_length))
+	if (crtc_state_is_legacy_gamma(crtc_state))
 		return 0;
 
 	/*
-	 * We also allow no degamma lut/ctm and a gamma lut at the legacy
-	 * size (256 entries).
+	 * We allow both degamma & gamma luts at the right size or
+	 * NULL.
 	 */
-	if (crtc_state_is_legacy_gamma(crtc_state))
-		return 0;
+	if (crtc_state->degamma_lut &&
+	    crtc_state->degamma_lut->length != degamma_length) {
+		DRM_DEBUG_KMS("invalid degamma LUT size %zu (expected %zu)\n",
+			      crtc_state->degamma_lut->length, degamma_length);
+		return -EINVAL;
+	}
+
+	if (crtc_state->gamma_lut &&
+	    crtc_state->gamma_lut->length != gamma_length) {
+		DRM_DEBUG_KMS("invalid gamma LUT size %zu (expected %zu)\n",
+			      crtc_state->gamma_lut->length, gamma_length);
+		return -EINVAL;
+	}
 
-	return -EINVAL;
+	return 0;
 }
 
 void intel_color_init(struct drm_crtc *crtc)
@@ -665,7 +673,7 @@ void intel_color_init(struct drm_crtc *crtc)
 	}
 
 	/* Enable color management support when we have degamma & gamma LUTs. */
-	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 &&
+	if (INTEL_INFO(dev_priv)->color.degamma_lut_size != 0 ||
 	    INTEL_INFO(dev_priv)->color.gamma_lut_size != 0)
 		drm_crtc_enable_color_mgmt(crtc,
 					   INTEL_INFO(dev_priv)->color.degamma_lut_size,

drivers/gpu/drm/i915/intel_hdmi.c

@@ -111,6 +111,8 @@ static u32 hsw_infoframe_enable(unsigned int type)
 		return VIDEO_DIP_ENABLE_SPD_HSW;
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return VIDEO_DIP_ENABLE_VS_HSW;
+	case HDMI_INFOFRAME_TYPE_DRM:
+		return VIDEO_DIP_ENABLE_DRM_GLK;
 	default:
 		MISSING_CASE(type);
 		return 0;
@@ -132,6 +134,8 @@ hsw_dip_data_reg(struct drm_i915_private *dev_priv,
 		return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
 	case HDMI_INFOFRAME_TYPE_VENDOR:
 		return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
+	case HDMI_INFOFRAME_TYPE_DRM:
+		return GLK_TVIDEO_DIP_DRM_DATA(cpu_transcoder, i);
 	default:
 		MISSING_CASE(type);
 		return INVALID_MMIO_REG;
@@ -416,7 +420,8 @@ static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
 
 	return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		      VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+		      VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW|
+		      VIDEO_DIP_ENABLE_DRM_GLK);
 }
 
 /*
@@ -468,6 +473,10 @@ static void intel_hdmi_set_drm_infoframe(struct drm_encoder *encoder,
 	struct hdr_static_metadata *hdr_metadata;
 	int ret;
 
+	if (!conn_state->hdr_source_metadata_blob_ptr ||
+	    conn_state->hdr_source_metadata_blob_ptr->length == 0)
+		return;
+
 	hdr_metadata = (struct hdr_static_metadata *)
 		conn_state->hdr_source_metadata_blob_ptr->data;
 
@@ -862,7 +871,8 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
 
 	val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
 		 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
-		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
+		 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
+		 VIDEO_DIP_ENABLE_DRM_GLK);
 
 	if (!enable) {
 		I915_WRITE(reg, val);
@@ -879,9 +889,7 @@ static void hsw_set_infoframes(struct drm_encoder *encoder,
 	intel_hdmi_set_avi_infoframe(encoder, crtc_state);
 	intel_hdmi_set_spd_infoframe(encoder, crtc_state);
 	intel_hdmi_set_hdmi_infoframe(encoder, crtc_state, conn_state);
-
-	/* Set Dynamic Range and Mastering Infoframe if supported and changed */
-	if (conn_state->hdr_metadata_changed)
+	if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
 		intel_hdmi_set_drm_infoframe(encoder, crtc_state, conn_state);
 }