get ready for w11a_V0.753 release

- rtl/sys_gen/*/*.vhd: drop superfluous genlib call - rtl/sys_gen/*/*.vmfset: accomodate recent code changes - tools/bin/tbrun: show correct 'found count' in summary message - tools/dox/*.Doxyfile: push version to 0.753 - tools/src/librtools/Rtime.ipp: change list-init make some gcc happy
wfjm · Dec 29, 2018 · b8dfa6d · b8dfa6d
1 parent 0fe9cd8
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diff --git a/doc/CHANGELOG.md b/doc/CHANGELOG.md
@@ -2,6 +2,7 @@
 
 ### Table of contents
 - Current [HEAD](#user-content-head)
+- Release [w11a_V0.753](#user-content-w11a_V0.753)
 - Release [w11a_V0.752](#user-content-w11a_V0.752)
 - Release [w11a_V0.751](#user-content-w11a_V0.751)
 - Release [w11a_V0.75](#user-content-w11a_V0.75)
@@ -19,6 +20,9 @@ The HEAD version shows the current development. No guarantees that
 software or firmware builds or that the documentation is consistent.
 The full set of tests is only run for tagged releases.
 
+<!-- --------------------------------------------------------------------- -->
+---
+## <a id="w11a_V0.753">2018-12-29: [w11a_V0.753](https://github.com/wfjm/w11/releases/tag/w11a_V0.753) - rev 1096(wfjm)</a>
 ### Summary
 - add continuous integration support via [Travis CI](https://travis-ci.org),
   add [project wfjm/w11](https://travis-ci.org/wfjm/w11), and setup
@@ -60,44 +64,49 @@ The full set of tests is only run for tagged releases.
   - generates create_disk compatible test patterns
 
 ### Changes
-- remove ISE 14.x build support for 7Series (mostly nexys4 designs)
-- Makefile: `make all_tcl` now quiet, use setup_packages_filt
-- vbomconv: now allows to inject Tcl scripts into the vivado project setup
-  sequence via the `@tcl` directive.
-- sys_w11_n4: reduce cache from 64 to 32 kB to keep timing closure
-- changes for DM_STAT_* signals (debug and monitoring)
-  - DM_STAT_SE: add elements cpbusy,idec,pcload,itimer
-  - DM_STAT_CA: added, used for cache monitoring
-  - DM_STAT_SY: removed, now replaced by DM_STAT_CA
-  - DM_STAT_EXP: added, for signals exported by pdp11_sys70
-- pdp11_sys70:
-  - instantiate pdp11_dmpcnt, setup performance counter sigs
-  - drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
-- pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload,itimer), drop ITIMER
-- pdp11_cache: drop CHIT, add DM_STAT_CA port, add detailed monitoring
-- pdp11_tmu(_sb): use DM_STAT_CA instead of DM_STAT_SY
-- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
-- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- sfs_gsim_core: new common simulation core
-  - use in {dcm,s6_cmt,s7_cmt}_sfs_gsim simulation models
-  - use in rtl/bplib/*/tb/tb_* test benches
-  - remove s7_cmt_sfs_tb
-- tbcore_rlink: wait 40 cycles after CONF_DONE
-- serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
+- general
+  - remove ISE 14.x build support for 7Series (mostly nexys4 designs)
+  - Makefile: `make all_tcl` now quiet, use setup_packages_filt
 - tools changes
+  - vbomconv: now allows to inject Tcl scripts into the vivado project setup
+    sequence via the `@tcl` directive.
   - xviv_msg_filter
     - display INFO Common 17-14 'further message disabled'
     - add c type rules for 'count-only' filters
     - add support for bitstream generation checking ([bit] section)
-  - tbrun: add --all option
+  - tbrun:
+    - add --all option
+    - show correct 'found count' in summary message
   - (all perl scripts): add and use bailout instead of die
   - viv_tools_build.tcl: increase message limits (all 200, some 5000)
-- tbench changes:
+  - rw11/shell.tcl: add workaround for tclreadline and `after` interference
+- firmware changes
+  - sys_w11_n4: reduce cache from 64 to 32 kB to keep timing closure
+  - changes for DM_STAT_* signals (debug and monitoring)
+    - DM_STAT_SE: add elements cpbusy,idec,pcload,itimer
+    - DM_STAT_CA: added, used for cache monitoring
+    - DM_STAT_SY: removed, now replaced by DM_STAT_CA
+    - DM_STAT_EXP: added, for signals exported by pdp11_sys70
+  - pdp11_sys70:
+    - instantiate pdp11_dmpcnt, setup performance counter sigs
+    - drop ITIMER,DM_STAT_DP, use DM_STAT_EXP, add PERFEXT port
+  - pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload,itimer), drop ITIMER
+  - pdp11_cache: drop CHIT, add DM_STAT_CA port, add detailed monitoring
+  - pdp11_tmu(_sb): use DM_STAT_CA instead of DM_STAT_SY
+  - ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
+  - sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
+  - sfs_gsim_core: new common simulation core
+    - use in {dcm,s6_cmt,s7_cmt}_sfs_gsim simulation models
+    - use in rtl/bplib/*/tb/tb_* test benches
+    - remove s7_cmt_sfs_tb
+  - tbcore_rlink: wait 40 cycles after CONF_DONE
+  - serport_master_tb: add 100 ps RXSD,TXSD delay to allow clock jitter
+- tbench changes
   - tst_sram: don't test memory controller reset anymore
 - backend changes
   - RtclRw11Unit: fix for clang: M_virt() now public
   - Rw11VirtDisk: keep track of disk geometry
-- backend code review:
+- backend code review
   - use for C++ compiles `-Wpedantic` (in addition to `-Wall` and `-Wextra`)
   - fixes for uninitialized variables (coverity, all uncritical)
   - catch exceptions in dtors (coverity, use Catch2Cerr)
@@ -136,7 +145,6 @@ The full set of tests is only run for tagged releases.
     - use =delete for noncopyable instead of boost
   - reduce usage of pointers in APIs
     - add HasPort/HasVirt(); Port() and Virt() return reference
-- rw11/shell.tcl: add workaround for tclreadline and `after` interference
 
 ### Bug Fixes
 - RtclArgs.hpp: BUGFIX: get *_min limits correct (gcc -Wpedantic)

diff --git a/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd b/rtl/bplib/bpgen/s7_cmt_1ce1ce.vhd
@@ -1,4 +1,4 @@
--- $Id: s7_cmt_1ce1ce.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: s7_cmt_1ce1ce.vhd 1091 2018-12-23 12:38:29Z mueller $
 --
 -- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -99,7 +99,7 @@ begin
       CE_MSEC => CE0_MSEC
     );
 
-  GEN_CLK1 : s7_cmt_sfs                 -- clock generator serport------------
+  GEN_CLK1 : s7_cmt_sfs                 -- clock generator serport -----------
     generic map (
       VCO_DIVIDE     => CLK1_VCODIV,
       VCO_MULTIPLY   => CLK1_VCOMUL,

diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../bplib/bpgen/bpgenlib.vbom
 ../tst_serlooplib.vbom
 ../../../vlib/serport/serportlib.vbom

diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_tst_serloop2_n4.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_tst_serloop2_n4.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -44,7 +44,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.bpgenlib.all;
 use work.tst_serlooplib.all;
 use work.serportlib.all;

diff --git a/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset b/rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_tst_serloop2_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
+# $Id: sys_tst_serloop2_n4.vmfset 1097 2018-12-29 11:20:14Z mueller $
 #
 # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 [syn]
@@ -37,8 +37,8 @@ I [Synth 8-6014] _reg                                           # generic
 
 # unused sequential element ------------------------------------
 I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*]               # generic
-# --> currently CDUWIDTH=8, but clock below 127 MHz             # OK 2016-06-05
-i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[ucnt][7]
+# --> currently CDUWIDTH=8, but clock below 127 MHz             # OK 2018-12-29
+i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[ucnt][7]
 # --> many HIO pins not used                                    # OK 2016-06-05
 i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
 i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]

diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../bplib/bpgen/bpgenlib.vbom
 ../tst_serlooplib.vbom
 ../../../vlib/serport/serportlib.vbom

diff --git a/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd b/rtl/sys_gen/tst_serloop/nexys4d/sys_tst_serloop2_n4d.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_tst_serloop2_n4d.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_tst_serloop2_n4d.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -43,7 +43,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.bpgenlib.all;
 use work.tst_serlooplib.all;
 use work.serportlib.all;

diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_tst_sram_c7.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_tst_sram_c7.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -47,7 +47,6 @@ use ieee.numeric_std.all;
 
 use work.slvtypes.all;
 use work.xlib.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset b/rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_tst_sram_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
+# $Id: sys_tst_sram_c7.vmfset 1097 2018-12-29 11:20:14Z mueller $
 #
 # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 [syn]
@@ -44,10 +44,10 @@ i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
 i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
 # --> only RB_STAT 0,1 used by tst_sram                         # OK 2017-06-11
 i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)]
-# --> CE_USEC isn't used (also not in rlink_sp2c)               # OK 2017-06-11
-i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec]
-# --> CES_USEC isn't used                                       # OK 2017-06-11
-i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
+# --> CE_USEC isn't used (also not in rlink_sp2c)               # OK 2018-12-29
+i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[usec]
+# --> CES_USEC isn't used                                       # OK 2018-12-29
+i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]
 
 {2018.1:}
 I [Synth 8-3332] R_LREGS_reg[attn][\d*]                         # generic

diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_tst_sram_n4.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_tst_sram_n4.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -58,7 +58,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset b/rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_tst_sram_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
+# $Id: sys_tst_sram_n4.vmfset 1097 2018-12-29 11:20:14Z mueller $
 #
 # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 [syn]
@@ -45,10 +45,10 @@ i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
 i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
 # --> only RB_STAT 0,1 used by tst_sram                         # OK 2016-06-05
 i [Synth 8-3332] RLINK/CORE/RL/R_BREGS_reg[stat][(2|3)]
-# --> CE_USEC isn't used (also not in rlink_sp2c)               # OK 2016-06-05
-i [Synth 8-3332] CLKDIV_CLK/R_REGS_reg[usec]
-# --> CES_USEC isn't used                                       # OK 2016-06-05
-i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
+# --> CE_USEC isn't used (also not in rlink_sp2c)               # OK 2018-12-29
+i [Synth 8-3332] CLKALL/DIV_CLK0/R_REGS_reg[usec]
+# --> CES_USEC isn't used                                       # OK 2018-12-29
+i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]
 
 {2018.1:}
 # --> monitor outputs moneop,monattn currently not used         # OK 2018-08-12

diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd b/rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_br_arty.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_w11a_br_arty.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -111,7 +111,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd b/rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_br_as7.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_w11a_br_as7.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -93,7 +93,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_b3.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_w11a_b3.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -113,7 +113,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 use work.slvtypes.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset b/rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_w11a_b3.vmfset 1091 2018-12-23 12:38:29Z mueller $
+# $Id: sys_w11a_b3.vmfset 1097 2018-12-29 11:20:14Z mueller $
 #
 # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 [syn]
@@ -83,8 +83,8 @@ i [Synth 8-3332] SEQ/SNUM0.R_VMWAIT_reg
 {2017.1:}
 I [Synth 8-3332] R_LREGS_reg[attn][\d*]                         # generic
 I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*]               # generic
-# --> usec not used for serport clock domain                    # OK 2017-06-06
-i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
+# --> usec not used for serport clock domain                    # OK 2018-12-29
+i [Synth 8-3332] R_REGS_reg[usec].* s7_cmt_1ce1ce
 # --> not yet used                                              # OK 2017-06-06
 i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
 # --> mawidth=4, nblock=11, so some cellen unused               # OK 2016-06-05

diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom
@@ -1,7 +1,6 @@
 # libs
 ../../../vlib/slvtypes.vhd
 ../../../vlib/xlib/xlib.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd

diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
@@ -1,4 +1,4 @@
--- $Id: sys_w11a_c7.vhd 1086 2018-12-16 18:29:55Z mueller $
+-- $Id: sys_w11a_c7.vhd 1094 2018-12-27 15:18:27Z mueller $
 --
 -- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -63,7 +63,6 @@ use ieee.numeric_std.all;
 
 use work.slvtypes.all;
 use work.xlib.all;
-use work.genlib.all;
 use work.serportlib.all;
 use work.rblib.all;
 use work.rbdlib.all;

diff --git a/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset b/rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
@@ -1,4 +1,4 @@
-# $Id: sys_w11a_c7.vmfset 1091 2018-12-23 12:38:29Z mueller $
+# $Id: sys_w11a_c7.vmfset 1097 2018-12-29 11:20:14Z mueller $
 #
 # ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 [syn]
@@ -112,8 +112,8 @@ i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
 i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
 
 {2017.1:2017.4}
-# --> usec not used for serport clock domain                    # OK 2017-06-24
-i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
+# --> usec not used for serport clock domain                    # OK 2018-12-29
+i [Synth 8-3332] R_REGS_reg[usec].* s7_cmt_1ce1ce
 # --> monitor outputs moneop,monattn currently not used         # OK 2017-06-24
 i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
 i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c

diff --git a/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom b/rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom
@@ -1,6 +1,5 @@
 # libs
 ../../../vlib/slvtypes.vhd
-../../../vlib/genlib/genlib.vhd
 ../../../vlib/serport/serportlib.vbom
 ../../../vlib/rbus/rblib.vhd
 ../../../vlib/rbus/rbdlib.vhd