Verilator overview

Verilator is a compiler that let you compile C++ and Verilog code to do simulations. Using C++ can be helpful to introduce new abstractions and speed up simulation time. The aim of this book however is to explore Verilator to learn and experiment with digital circuits. This book can also be read online at gitbooks

Learning Verilog

While Verilator let you write models in C++, you also need to know how to use Verilog.

Verilog courses and tutorials

Here are some places where you can learn about Verilog such as:

• Hardware Description Languages for FPGA Design - This course introduces the languages, discusses a number of interesting code examples, and let you simulate these
• ChipVerify Verilog webpage
• ASIC world Verilog webpages
• OpenCores

Also, the Icarus Verilog simulator is a good simulator to learn Verilog and it is free. In the Coursera course Hardware Description Languages for FPGA Design, the Mentor Graphics ModelSim simulator is used which is a tool also used by many companies.

VHDL vs Verilog

Besides Verilog, VHDL can be useful to know when designing digital systems. We will not look into VHDL here, but if you are curious here are some places:

• LED Displays Course - Basic introduction to electronics and digital systems

Verilator repository

The Verilator repository can be found here

{% hint style="info" %} Verilator runs on Unix and with Mingsys on Windows. {% endhint %}

Good places to start learning Verilator are also:

• Verilator manual
• Verilator reference list
• UART example for ZipCPU

Notes on this Gitbook

This book is Work in Progress. Feel free to add ideas and feedback by creating an issue on Github.