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Add Intel XED as decoder/disassembler #33

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hlide opened this issue Aug 6, 2017 · 2 comments
Open

Add Intel XED as decoder/disassembler #33

hlide opened this issue Aug 6, 2017 · 2 comments

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@hlide
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hlide commented Aug 6, 2017

Source at https://github.com/intelxed/xed. Version 3.

XED being a complete encoder/decoder for every architecture including AMD, KNC, KNL.

For instance, it can give details on some unofficial instructions:

{
ICLASS    : SALC
CPL       : 3
CATEGORY  : FLAGOP
EXTENSION : BASE
ISA_SET   : I86
FLAGS     : MUST [ cf-tst ]
PATTERN   : 0xD6 not64
OPERANDS  : REG0=XED_REG_AL:w:SUPP
COMMENT   : UNDOC - "The Undocumented PC", 2nd ed 1997, says it is present on all Intel CPUs of that time.
}
{
ICLASS    : INT1
CPL       : 3
CATEGORY  : INTERRUPT
EXTENSION : BASE
ISA_SET   : I86
PATTERN   : 0xF1
OPERANDS  : REG0=rIP():w:SUPP
COMMENT   : UNDOC by Intel, but in AMD's opcode map
}
{
ICLASS    : FSETPM287_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b100]
OPERANDS  :
COMMENT   : UNDOC
}
{
ICLASS    : FENI8087_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b000]
OPERANDS  :
COMMENT   : UNDOC
}
{
ICLASS    : FDISI8087_NOP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: NOP NOTSX
PATTERN   : 0xDB MOD[0b11] MOD=3 REG[0b100] RM[0b001]
COMMENT   : UNDOC
OPERANDS  :
}
{
ICLASS    : FFREEP
CPL       : 3
CATEGORY  : X87_ALU
EXTENSION : X87
ATTRIBUTES: X87_CONTROL NOTSX
FLAGS     : MUST [ fc0-u   fc1-u   fc2-u   fc3-u   ]
PATTERN   : 0xDF MOD[0b11] MOD=3 REG[0b000] RM[nnn]
OPERANDS  : REG0=X87():r:f80 REG1=XED_REG_X87TAG:w:SUPP REG2=XED_REG_X87POP:r:SUPP
COMMENT   : UNDOC
}

and so on.

@hlide
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hlide commented Aug 6, 2017

Case of near JMP:

{
ICLASS    : JMP
CPL       : 3
CATEGORY  : UNCOND_BR
EXTENSION : BASE
ISA_SET   : I86
ATTRIBUTES: MPX_PREFIX_ABLE
PATTERN   : 0xE9 not64 BRDISPz()
OPERANDS  : RELBR:r:z REG0=XED_REG_EIP:rw:SUPP
PATTERN   : 0xE9 mode64 FORCE64() BRDISP32()
OPERANDS  : RELBR:r:d REG0=XED_REG_RIP:rw:SUPP
}

it doesn't seem to apply the correct pattern for AMD though.

@jakob-engblom-i
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XED is probably the best source for Intel encodings of instructions.

Speaking for myself, not for my employer.

aengelke added a commit to aengelke/fadec that referenced this issue Jan 23, 2021
Undocumented instruction are not decoded by default.

- SALC: undocumented in any recent manual and unsupported by newer
  Intel CPUs. Including as listed by [1,2].
- Undocumented FPU instructions: see [2].

[1]: http://www.rcollins.org/secrets/opcodes/SALC.html
[2]: xoreaxeaxeax/sandsifter#33
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