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A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.

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Router Microarchitecture

A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA with 150MHz frequency.

1. NoC Architecture

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PE: send data and receive data to and from other PEs. Date stored in BRAM.

Ni: network interface

R: router

2. Router

5 pipelined stage:

  • route computation
  • data transformation and store in fifo
  • VC Allocation and Switch Allocation
  • Switch Traversal
  • Link Traversal

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Route computing algorithm: negative-first algorithm (dead-lock free)

VC: credit-based control

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switch channel allocation: Round-Robin and Queuing arbiter

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3. Result

  • transport 48*30 flits in 180 cycle, transmission density is 6.7 hops/cycle

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  • pll frequency: 150MHz

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  • High scalability and well seperate modules for testing more policies.

  • Can be applyed to multi-core computing for AI accelarating like matrix convolution, matrix multiplication used in neural networks.

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A 2D mesh Network on Chip with 5-stage pipelined router, all implemented in Verilog and run on Artix-7 FPGA.

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