integrated last word stuff

yangsu · Nov 27, 2012 · c6a1335 · c6a1335
1 parent 124cc1b
commit c6a1335
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Showing 3 changed files with 11 additions and 7 deletions.
diff --git a/inputProcessor.vhd b/inputProcessor.vhd
@@ -197,6 +197,8 @@ BEGIN
 	Stage13: computedCrcFifo PORT MAP (aclr OR signal_reset, clk25, signal_temp_crc2, data_in_valid AND signal_receiving, data_in_valid AND signal_receiving, signal_temp_crc3);
 	Stage14: computedCrcFifo PORT MAP (aclr OR signal_reset, clk25, signal_temp_crc3, data_in_valid AND signal_receiving, data_in_valid AND signal_receiving, signal_final_crc);
 
+
+
 	signal_length_and_crc_buffer_input(10 DOWNTO 0) <= signal_frame_counter_length(10 DOWNTO 0);
 	signal_length_and_crc_buffer_input(11) <= crc_valid;
 
@@ -206,7 +208,8 @@ BEGIN
 	crc_check_state <= signal_crc_check;
 
 	shifter: lastWordShifter PORT MAP (aclr, clk25, data_in, signal_shifter);
-	last_word <= signal_final_crc;
+
+	last_word <= signal_shifter;
 
 	crc_valid <= '1' WHEN (signal_shifter XOR signal_crc) = "11111111111111111111111111111111" ELSE '0';
 	--crc_valid <= '0' WHEN (signal_shifter XOR signal_crc) = "11111111111111111111111111111111" ELSE '1';

diff --git a/lastWordShifter.vhd b/lastWordShifter.vhd
@@ -26,28 +26,28 @@ ARCHITECTURE arch OF lastWordShifter IS
 	SIGNAL out0, out1, out2, out3 : STD_LOGIC_VECTOR(7 DOWNTO 0);
 
 BEGIN
-	shifter0: fifo8dc PORT MAP (
+	shifter0: shiftReg8Bit PORT MAP (
 		aclr		=>	aclr,
 		clock		=>	clk,
 		shiftin =>	data_in(0),
 		q				=>	out0
 	);
 
-	shifter1: fifo8dc PORT MAP (
+	shifter1: shiftReg8Bit PORT MAP (
 		aclr		=>	aclr,
 		clock		=>	clk,
 		shiftin =>	data_in(1),
 		q				=>	out1
 	);
 
-	shifter2: fifo8dc PORT MAP (
+	shifter2: shiftReg8Bit PORT MAP (
 		aclr		=>	aclr,
 		clock		=>	clk,
 		shiftin =>	data_in(2),
 		q				=>	out2
 	);
 
-	shifter3: fifo8dc PORT MAP (
+	shifter3: shiftReg8Bit PORT MAP (
 		aclr		=>	aclr,
 		clock		=>	clk,
 		shiftin =>	data_in(3),

diff --git a/receive.qsf b/receive.qsf
@@ -55,7 +55,7 @@ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
 set_instance_assignment -name CLOCK_SETTINGS "Clock 25" -to clk25
 set_instance_assignment -name CLOCK_SETTINGS "Clock 50" -to clk50
 set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE receiveTest.vwf
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name VHDL_FILE lastWordShifter.vhd
 set_global_assignment -name VHDL_FILE shiftReg8Bit.vhd
 set_global_assignment -name VECTOR_WAVEFORM_FILE receiveTest.vwf
 set_global_assignment -name MIF_FILE framemem.mif
@@ -97,4 +97,5 @@ set_global_assignment -name QIP_FILE register12bit.qip
 set_global_assignment -name QIP_FILE lengthBuffer.qip
 set_global_assignment -name QIP_FILE lengthAndCrcBuffer.qip
 set_global_assignment -name QIP_FILE computedCrcShifter.qip
-set_global_assignment -name QIP_FILE computedCrcFifo.qip
+set_global_assignment -name QIP_FILE computedCrcFifo.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top