icepll -m output has trailing comma in port list

[joshhead]

When icepll saves PLL configuration as a module, it includes a comma after the last port in the port list.

Yosys synthesizes it with no problems, but Icarus Verilog considers the extra comma a syntax error.

Would it be better to remove the comma after .PLLOUTCORE(clock_out)?

$ icepll -m -f pll.v

F_PLLIN:    12.000 MHz (given)
F_PLLOUT:   60.000 MHz (requested)
F_PLLOUT:   67.500 MHz (achieved)

FEEDBACK: SIMPLE
F_PFD:   12.000 MHz
F_VCO:  540.000 MHz

DIVR:  0 (4'b0000)
DIVF: 44 (7'b0101100)
DIVQ:  3 (3'b011)

FILTER_RANGE: 1 (3'b001)

PLL configuration written to: pll.v

pll.v

/**
 * PLL configuration
 *
 * This Verilog module was generated automatically
 * using the icepll tool from the IceStorm project.
 * Use at your own risk.
 *
 * Given input frequency:        12.000 MHz
 * Requested output frequency:   60.000 MHz
 * Achieved output frequency:    67.500 MHz
 */

module pll(
	input  clock_in,
	output clock_out,
	output locked
	);

SB_PLL40_CORE #(
		.FEEDBACK_PATH("SIMPLE"),
		.DIVR(4'b0000),		// DIVR =  0
		.DIVF(7'b0101100),	// DIVF = 44
		.DIVQ(3'b011),		// DIVQ =  3
		.FILTER_RANGE(3'b001)	// FILTER_RANGE = 1
	) uut (
		.LOCK(locked),
		.RESETB(1'b1),
		.BYPASS(1'b0),
		.REFERENCECLK(clock_in),
		.PLLOUTCORE(clock_out),
		);

endmodule

$ iverilog -t null pll.v /usr/local/share/yosys/ice40/cells_sim.v
pll.v:31: syntax error
pll.v:25: error: Syntax error in instance port expression(s).

[cliffordwolf]

Fixed by #75