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EDIF backend result rejected by Xilinx #14

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jameswalmsley opened this issue Nov 3, 2013 · 3 comments
Closed

EDIF backend result rejected by Xilinx #14

jameswalmsley opened this issue Nov 3, 2013 · 3 comments

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@jameswalmsley
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module hadder(a, b, s, c);

   input a, b;
   output s, c;

  assign s = a ^ b;
  assign c = a & b;

endmodule


module top(a, b, led_7, led_6, led_5, led_4, led_3, led_2, led_1, led_0);

    input a, b;
    output led_7, led_6, led_5, led_4;
    output led_3, led_2, led_1, led_0;

   hadder u0 (
                          a,
                          b,
                          led_0,
                          led_1
                          );

   assign {led_7, led_6, led_5, led_4, led_3, led_2} = 0;

endmodule; // top

Synthesising the above code resulted in:

+ /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/edif2ngd -a synth.edif synth.ngo
Release 14.7 - edif2ngd P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
INFO:NgdBuild - Release 14.7 edif2ngd P.20131013 (lin64)
INFO:NgdBuild - Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
ERROR:NgdBuild:196 - On or above line 148 in file "synth.edif":  Problem parsing
   "rename".  This likely means that the EDIF netlist was improperly written. 
   Please contact the vendor of the program that produced this EDIF.
@jameswalmsley
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If I comment out the hadder u0 instantiation, then the edif produced is correct, and accepted by the Xilinx toolchain.

@jameswalmsley
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Ok, thanks for adding the feature, i'll continue my tutorial on adders now.

@cliffordwolf
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The problem here was that the instantiation of hadder used positional arguments and edif does not. I've now added a feature to the hierarchy pass (enabled by default) that transforms positional arguments to arguments using the proper port names. It seems to work now (tested with ISE 14.5).

Interestingly, if I don't use synth_xilinx but instead simply write the RTL netlist to the EDIF file, edif2ngd just segfaults with any useful error message. Maybe because the netlist contains cell types that the Xilinx tools do not recognize? I'm not going to further investigate this, but it does not improve the level of confidence I have in edif2ngd.. ;-)

mkurc-ant referenced this issue in antmicro/yosys Sep 10, 2020
mkurc-ant referenced this issue in antmicro/yosys Sep 10, 2020
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