fix sw

yttnn · Apr 5, 2024 · f36f35e · f36f35e
1 parent 46a3693
commit f36f35e
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Showing 2 changed files with 6 additions and 1 deletion.
diff --git a/core/core.sv b/core/core.sv
@@ -224,6 +224,11 @@ module core (
           if (is_csr || is_ecall) begin
             csr_regs[csr_addr] <= csr_wdata;
           end
+          `ifdef DEBUG
+          if (is_store) begin
+            $display("store mem[%h]=%h", load_store_addr, mem_wdata);
+          end
+          `endif
           state <= WB;
         end
         WB : begin

diff --git a/core/memory.sv b/core/memory.sv
@@ -111,7 +111,7 @@ module memory (
       mem_rdata <= MEM[mem_addr[31:2]];
     end
     else if (mem_w_enable) begin
-      MEM[mem_addr] <= mem_wdata;
+      MEM[mem_addr[31:2]] <= mem_wdata;
     end
   end