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drivers: interrupt_controller: add LiteX interrupt controller driver
Add LiteX interrupt controller driver and bindings for this device. Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com> Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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/* | ||
* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com> | ||
* | ||
* SPDX-License-Identifier: Apache-2.0 | ||
*/ | ||
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#include <kernel.h> | ||
#include <arch/cpu.h> | ||
#include <init.h> | ||
#include <irq.h> | ||
#include <device.h> | ||
#include <zephyr.h> | ||
#include <zephyr/types.h> | ||
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#define IRQ_MASK DT_VEXRISCV_INTC0_0_IRQ_MASK_BASE_ADDRESS | ||
#define IRQ_PENDING DT_VEXRISCV_INTC0_0_IRQ_PENDING_BASE_ADDRESS | ||
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#define TIMER0_IRQ DT_LITEX_TIMER0_E0002800_IRQ_0 | ||
#define UART0_IRQ DT_LITEX_UART0_E0001800_IRQ_0 | ||
static inline void vexriscv_litex_irq_setmask(u32_t mask) | ||
{ | ||
__asm__ volatile ("csrw %0, %1" :: "i"(IRQ_MASK), "r"(mask)); | ||
} | ||
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static inline u32_t vexriscv_litex_irq_getmask(void) | ||
{ | ||
u32_t mask; | ||
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__asm__ volatile ("csrr %0, %1" : "=r"(mask) : "i"(IRQ_MASK)); | ||
return mask; | ||
} | ||
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static inline u32_t vexriscv_litex_irq_pending(void) | ||
{ | ||
u32_t pending; | ||
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__asm__ volatile ("csrr %0, %1" : "=r"(pending) : "i"(IRQ_PENDING)); | ||
return pending; | ||
} | ||
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static inline void vexriscv_litex_irq_setie(u32_t ie) | ||
{ | ||
if (ie) { | ||
__asm__ volatile ("csrrs x0, mstatus, %0" | ||
:: "r"(SOC_MSTATUS_IEN)); | ||
} else { | ||
__asm__ volatile ("csrrc x0, mstatus, %0" | ||
:: "r"(SOC_MSTATUS_IEN)); | ||
} | ||
} | ||
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static void vexriscv_litex_irq_handler(void *device) | ||
{ | ||
struct _isr_table_entry *ite; | ||
u32_t pending, mask, irqs; | ||
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pending = vexriscv_litex_irq_pending(); | ||
mask = vexriscv_litex_irq_getmask(); | ||
irqs = pending & mask; | ||
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#ifdef CONFIG_LITEX_TIMER | ||
if (irqs & (1 << TIMER0_IRQ)) { | ||
ite = &_sw_isr_table[TIMER0_IRQ]; | ||
ite->isr(ite->arg); | ||
} | ||
#endif | ||
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN | ||
if (irqs & (1 << UART0_IRQ)) { | ||
ite = &_sw_isr_table[UART0_IRQ]; | ||
ite->isr(ite->arg); | ||
} | ||
#endif | ||
} | ||
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void z_arch_irq_enable(unsigned int irq) | ||
{ | ||
vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() | (1 << irq)); | ||
} | ||
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void z_arch_irq_disable(unsigned int irq) | ||
{ | ||
vexriscv_litex_irq_setmask(vexriscv_litex_irq_getmask() & ~(1 << irq)); | ||
} | ||
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int z_arch_irq_is_enabled(unsigned int irq) | ||
{ | ||
return vexriscv_litex_irq_getmask() & (1 << irq); | ||
} | ||
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static int vexriscv_litex_irq_init(struct device *dev) | ||
{ | ||
ARG_UNUSED(dev); | ||
__asm__ volatile ("csrrs x0, mie, %0" | ||
:: "r"((1 << RISCV_MACHINE_TIMER_IRQ) | ||
| (1 << RISCV_MACHINE_EXT_IRQ))); | ||
vexriscv_litex_irq_setie(1); | ||
IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ, 0, vexriscv_litex_irq_handler, | ||
NULL, 0); | ||
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return 0; | ||
} | ||
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SYS_INIT(vexriscv_litex_irq_init, PRE_KERNEL_2, | ||
CONFIG_KERNEL_INIT_PRIORITY_DEFAULT); |
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# | ||
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com> | ||
# | ||
# SPDX-License-Identifier: Apache-2.0 | ||
# | ||
--- | ||
title: LiteX VexRiscV Interrupt Controller | ||
version: 0.1 | ||
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description: > | ||
This binding describes LiteX VexRiscV Interrupt Controller | ||
properties: | ||
compatible: | ||
category: required | ||
type: string | ||
description: compatible strings | ||
constraint: "vexriscv,intc0" | ||
generation: define | ||
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reg: | ||
category: required | ||
type: int | ||
description: mmio register space | ||
generation: define | ||
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riscv,max-priority: | ||
type: int | ||
description: maximum interrupt priority | ||
category: required | ||
generation: define | ||
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"#cells": | ||
- irq | ||
- priority | ||
... |