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drivers: timer: add LiteX timer driver

Add LiteX timer driver with bindings for this device.

Signed-off-by: Filip Kokosinski <fkokosinski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
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fkokosinski authored and galak committed Mar 28, 2019
1 parent b373916 commit c0c3cdfc57844ce3f7fb6cd2d2f50d1bb096c958
@@ -146,6 +146,7 @@
/drivers/timer/cortex_m_systick.c @ioannisg
/drivers/timer/altera_avalon_timer_hal.c @wentongwu
/drivers/timer/riscv_machine_timer.c @nategraff-sifive @kgugala @pgielda
/drivers/timer/litex_timer.c @mateusz-holenko @kgugala @pgielda
/drivers/usb/ @jfischer-phytec-iot @finikorg
/drivers/usb/device/usb_dc_stm32.c @ydamigos @loicpoulain
/drivers/i2c/i2c_ll_stm32* @ldts @ydamigos
@@ -12,3 +12,4 @@ zephyr_sources_if_kconfig( cortex_m_systick.c)
zephyr_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
zephyr_sources_if_kconfig( native_posix_timer.c)
zephyr_sources_if_kconfig( sam0_rtc_timer.c)
zephyr_sources_if_kconfig( litex_timer.c)
@@ -136,6 +136,14 @@ config RV32M1_LPTMR_TIMER
peripheral as the system clock. It provides the standard "system clock
driver" interfaces.

config LITEX_TIMER
bool "LiteX Timer"
default y
depends on !TICKLESS_IDLE
depends on SOC_RISCV32_LITEX_VEXRISCV
help
This module implements a kernel device driver for LiteX Timer.

config NATIVE_POSIX_TIMER
bool "(POSIX) native_posix timer driver"
default y
@@ -0,0 +1,73 @@
/*
* Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
*
* SPDX-License-Identifier: Apache-2.0
*/

#include <kernel.h>
#include <arch/cpu.h>
#include <device.h>
#include <irq.h>
#include <system_timer.h>

#define TIMER_BASE DT_LITEX_TIMER0_E0002800_BASE_ADDRESS
#define TIMER_LOAD_ADDR ((TIMER_BASE) + 0x00)
#define TIMER_RELOAD_ADDR ((TIMER_BASE) + 0x10)
#define TIMER_EN_ADDR ((TIMER_BASE) + 0x20)
#define TIMER_EV_PENDING_ADDR ((TIMER_BASE) + 0x3c)
#define TIMER_EV_ENABLE_ADDR ((TIMER_BASE) + 0x40)

#define TIMER_EV 0x1
#define TIMER_IRQ DT_LITEX_TIMER0_E0002800_IRQ_0
#define TIMER_DISABLE 0x0
#define TIMER_ENABLE 0x1
#define TIMER_VALUE ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) / 100)


static u32_t accumulated_cycle_count;

static void litex_timer_irq_handler(void *device)
{
ARG_UNUSED(device);
int key = irq_lock();

sys_write8(TIMER_EV, TIMER_EV_PENDING_ADDR);
accumulated_cycle_count += sys_clock_hw_cycles_per_tick();
z_clock_announce(1);

irq_unlock(key);
}

u32_t z_timer_cycle_get_32(void)
{
return accumulated_cycle_count;
}

/* tickless kernel is not supported */
u32_t z_clock_elapsed(void)
{
return 0;
}

int z_clock_driver_init(struct device *device)
{
ARG_UNUSED(device);
IRQ_CONNECT(TIMER_IRQ, DT_LITEX_TIMER0_E0002800_IRQ_0_PRIORITY,
litex_timer_irq_handler, NULL, 0);
irq_enable(TIMER_IRQ);

sys_write8(TIMER_DISABLE, TIMER_EN_ADDR);

for (int i = 0; i < 4; i++) {
sys_write8(TIMER_VALUE >> (24 - i * 8),
TIMER_RELOAD_ADDR + i * 0x4);
sys_write8(TIMER_VALUE >> (24 - i * 8),
TIMER_LOAD_ADDR + i * 0x4);
}

sys_write8(TIMER_ENABLE, TIMER_EN_ADDR);
sys_write8(sys_read8(TIMER_EV_PENDING_ADDR), TIMER_EV_PENDING_ADDR);
sys_write8(TIMER_EV, TIMER_EV_ENABLE_ADDR);

return 0;
}
@@ -0,0 +1,31 @@
#
# Copyright (c) 2018 - 2019 Antmicro <www.antmicro.com>
#
# SPDX-License-Identifier: Apache-2.0
#
---
title: LiteX timer
version: 0.1

description: >
This binding gives a base representation of the LiteX timer
properties:
compatible:
type: string
category: required
description: compatible strings
constraint: "litex,timer0"

reg:
type: array
description: mmio register space
generation: define
category: required

interrupts:
type: array
category: required
description: required interrupts
generation: define
...
@@ -66,6 +66,8 @@
#define TICK_IRQ IRQ_TIMER0
#elif defined(CONFIG_RISCV_MACHINE_TIMER)
#define TICK_IRQ RISCV_MACHINE_TIMER_IRQ
#elif defined(CONFIG_LITEX_TIMER)
#define TICK_IRQ DT_LITEX_TIMER0_E0002800_IRQ_0
#elif defined(CONFIG_RV32M1_LPTMR_TIMER)
#define TICK_IRQ DT_OPENISA_RV32M1_LPTMR_SYSTEM_LPTMR_IRQ
#elif defined(CONFIG_CPU_CORTEX_M)

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