stm32f7: DTCM included in sram0 #15909
Labels
area: Devicetree
bug
The issue is a bug, or the PR is fixing a bug
platform: STM32
ST Micro STM32
priority: low
Low impact/importance bug
Describe the bug
The SRAM base address and sizes for the STM32F7 dts configs includes DTCM memory @ 0x20000000, but TCM is a different beast and probably shouldn't be lumped with in with SRAM.
Expected behavior
DTCM and ITCM require some special handling and have some special features. For the time being, use only SRAM1 and SRAM2.
A feature enhancement would be to enable ITCM and DTCM and make use of them.
Impact
May create subtle issues with DMA (LTDC, Ethernet, others fight with CPU). There may be issues with memory blocks that cross the DTCM/SRAM address.
Environment (please complete the following information):
STM32F7-based boards, at least.
Additional context
ST AN4667:
https://www.st.com/content/ccc/resource/technical/document/application_note/0e/53/06/68/ef/2f/4a/cd/DM00169764.pdf/files/DM00169764.pdf/jcr:content/translations/en.DM00169764.pdf
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