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tests/benchmarks/timing_info failed on mec15xxevb_assy6853 board. #23414

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chen-png opened this issue Mar 12, 2020 · 1 comment · Fixed by #23970
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tests/benchmarks/timing_info failed on mec15xxevb_assy6853 board. #23414

chen-png opened this issue Mar 12, 2020 · 1 comment · Fixed by #23970
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bug The issue is a bug, or the PR is fixing a bug priority: low Low impact/importance bug

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@chen-png
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Describe the bug
Running tests/benchmarks/timing_info on mec15xxevb_assy6853 board, the test result is incorrect, for example, the "Clock Frequency is 0 MHz".

To Reproduce
Steps to reproduce the behavior:

  1. sanitycheck --hardware-map ~/mec1.yml --device-testing -T tests/benchmarks/timing_info
  2. See error

Screenshots or console output
*** Booting Zephyr OS build zephyr-v2.2.0-219-g86bfc489f4a7 ***
starting test - Time Measurement

Timing Results: Clock Frequency: 0 MHz
Context switch : 0 cycles , 0 ns
Interrupt latency : 0 cycles , 0 ns
Tick overhead : 0 cycles , 0 ns
Thread Creation : 1 cycles , 30517 ns
Thread cancel : 0 cycles , 0 ns
Thread abort : 0 cycles , 0 ns
Thread Suspend : 1 cycles , 30517 ns
Thread Resume : 0 cycles , 0 ns
Thread Yield : 0 cycles , 0 ns
Thread Sleep : 1 cycles , 30517 ns
Heap Malloc : 0 cycles , 0 ns
Heap Free : 0 cycles , 0 ns
Semaphore Take with context switch : 0 cycles , 0 ns
Semaphore Give with context switch : 1 cycles , 30517 ns
Semaphore Take without context switch : 0 cycles , 0 ns
Semaphore Give without context switch : 1 cycles , 30517 ns
Mutex lock : 0 cycles , 0 ns
Mutex unlock : 0 cycles , 0 ns
Message Queue Put with context switch : 1 cycles , 30517 ns
Message Queue Put without context switch : 0 cycles , 0 ns
Message Queue get with context switch : 1 cycles , 30517 ns
Message Queue get without context switch : 0 cycles , 0 ns
MailBox synchronous put : 0 cycles , 0 ns
MailBox synchronous get : 1 cycles , 30517 ns
MailBox asynchronous put : 0 cycles , 0 ns

Environment (please complete the following information):

  • OS: fedora28
  • Toolchain: zephyr-sdk-0.11.1
  • Commit ID: 86bfc48
@chen-png chen-png added the bug The issue is a bug, or the PR is fixing a bug label Mar 12, 2020
@LeiW000
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LeiW000 commented Mar 13, 2020

The reason why some benchmark results in thetest cases is "0" is that "RTOS" Timer is used to calucate elapsed time. But "RTOS" timer is operated on 32kHz oscillator(Please refer to section 22 in the data sheet). It is impossible to reach "ns" precision with it. However, CPU core on the board runs on 48MHz.

We can enble the high percision timer (16/32 BIT BASIC TIMER--refer to section 19 in the data sheet) to resolve the issue. Someone has to wirte a driver for that timer.

The data sheet.
https://github.com/MicrochipTech/CPGZephyrDocs/blob/master/MEC1501/MEC1501_Datasheet.pdf

@nashif nashif added the priority: low Low impact/importance bug label Mar 31, 2020
dcpleung added a commit to dcpleung/zephyr that referenced this issue Mar 31, 2020
The timer counter for ticks on MEC1501 SoC is based on the RTOS
timer which runs at 32kHz. This is too slow for timing benchmarks
as most cases can be finished within one or two ticks. Since
the SoC has higher frequency timers running at 48MHz, add
the necessary bits to use these for timing benchmarks.

Fix zephyrproject-rtos#23414

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
nashif pushed a commit that referenced this issue Mar 31, 2020
The timer counter for ticks on MEC1501 SoC is based on the RTOS
timer which runs at 32kHz. This is too slow for timing benchmarks
as most cases can be finished within one or two ticks. Since
the SoC has higher frequency timers running at 48MHz, add
the necessary bits to use these for timing benchmarks.

Fix #23414

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
hakehuang pushed a commit to hakehuang/zephyr that referenced this issue Apr 30, 2020
The timer counter for ticks on MEC1501 SoC is based on the RTOS
timer which runs at 32kHz. This is too slow for timing benchmarks
as most cases can be finished within one or two ticks. Since
the SoC has higher frequency timers running at 48MHz, add
the necessary bits to use these for timing benchmarks.

Fix zephyrproject-rtos#23414

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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