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stm32h7: Transition clock configuration from Kconfig to device tree #34701

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merged 6 commits into from May 3, 2021
Merged

stm32h7: Transition clock configuration from Kconfig to device tree #34701

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7cc163e
dts/bindings: clocks: Add clocks bindings for stm32h7 series
erwango Apr 28, 2021
675a204
dts/arm/st: h7: Add clocks nodes
erwango Apr 29, 2021
6b997d8
include/drivers/clock_control: stm32: Bits for H7 dts clock config
erwango Apr 29, 2021
57bd9fe
drivers: clock_control: stm32h7: Use dts based configuration macros
erwango Apr 29, 2021
8b1a8b3
board: nucleo_h723zg: Convert to dts based clock configuration
erwango Apr 29, 2021
3da4829
board: nucleo_h745zi_q: Convert to dts based clock configuration
erwango Apr 29, 2021
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27 changes: 27 additions & 0 deletions boards/arm/nucleo_h723zg/nucleo_h723zg.dts
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Expand Up @@ -62,6 +62,33 @@
};
};

&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};

&pll {
div-m = <4>;
mul-n = <275>;
div-p = <1>;
div-q = <4>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(550)>;
d1cpre = <1>;
hpre = <2>; /* HCLK: 275 MHz */
d1ppre = <2>; /* APB1: 137.5 MHz */
d2ppre1 = <2>; /* APB2: 137.5 MHz */
d2ppre2 = <2>; /* APB3: 137.5 MHz */
d3ppre = <2>; /* APB4: 137.5 MHz */
};

&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
current-speed = <115200>;
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35 changes: 1 addition & 34 deletions boards/arm/nucleo_h723zg/nucleo_h723zg_defconfig
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Expand Up @@ -2,7 +2,6 @@

CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H723XX=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=550000000

CONFIG_BOARD_NUCLEO_H723ZG=y

Expand All @@ -25,37 +24,5 @@ CONFIG_PINMUX=y
# Enable GPIO
CONFIG_GPIO=y

# Clock Configuration
# Enable Clock
CONFIG_CLOCK_CONTROL=y

CONFIG_CLOCK_STM32_D1CPRE=1

# HCLK: 275MHz
CONFIG_CLOCK_STM32_HPRE=2

# APB1: 137.5MHz
CONFIG_CLOCK_STM32_D2PPRE1=2

# APB2: 137.5MHz
CONFIG_CLOCK_STM32_D2PPRE2=2

# APB3: 137.5MHz
CONFIG_CLOCK_STM32_D1PPRE=2

# APB4: 137.5MHz
CONFIG_CLOCK_STM32_D3PPRE=2

# STLINK provides 8MHz clock input
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# Use HSE (bypass) as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_BYPASS=y

# Produce 550MHz clock at PLL1 output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=275
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=4
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2
20 changes: 0 additions & 20 deletions boards/arm/nucleo_h745zi_q/Kconfig.defconfig
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Expand Up @@ -9,26 +9,6 @@ config BOARD
default "nucleo_h745zi_q_m7" if BOARD_NUCLEO_H745ZI_Q_M7
default "nucleo_h745zi_q_m4" if BOARD_NUCLEO_H745ZI_Q_M4

config CLOCK_STM32_D1CPRE
default 1

config CLOCK_STM32_HPRE
# HCLK: 240MHz
default 2

config CLOCK_STM32_D2PPRE1
# APBX: 120MHz
default 2

config CLOCK_STM32_D2PPRE2
default 2

config CLOCK_STM32_D1PPRE
default 2

config CLOCK_STM32_D3PPRE
default 2

config STM32H7_DUAL_CORE
default y

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9 changes: 9 additions & 0 deletions boards/arm/nucleo_h745zi_q/nucleo_h745zi_q.dtsi
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Expand Up @@ -28,3 +28,12 @@
};
};
};

&rcc {
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d1cpre = <1>;
hpre = <2>;
d1ppre = <2>;
d2ppre1 = <2>;
d2ppre2 = <2>;
d3ppre = <2>;
};
4 changes: 4 additions & 0 deletions boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4.dts
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Expand Up @@ -30,3 +30,7 @@
current-speed = <115200>;
status = "okay";
};

&rcc {
clock-frequency = <DT_FREQ_M(240)>;
};
4 changes: 1 addition & 3 deletions boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m4_defconfig
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Expand Up @@ -2,8 +2,6 @@

CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H745XX=y
# SYS_CLOCK_M4 = SYS_CLOCK_M7 / CLOCK_STM32_HPRE
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=240000000

# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_NUCLEO_H745ZI_Q_M4=y
Expand All @@ -14,7 +12,7 @@ CONFIG_PINMUX=y
# Enable GPIO
CONFIG_GPIO=y

# Clock Configuration
# Enable clock
CONFIG_CLOCK_CONTROL=y

# By default SERIAL peripherals are assigned to m7
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21 changes: 21 additions & 0 deletions boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7.dts
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Expand Up @@ -45,6 +45,27 @@
};
};

&clk_hse {
hse-bypass;
clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
status = "okay";
};

&pll {
div-m = <1>;
mul-n = <120>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(480)>;
};

&usart3 {
pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
current-speed = <115200>;
Expand Down
18 changes: 1 addition & 17 deletions boards/arm/nucleo_h745zi_q/nucleo_h745zi_q_m7_defconfig
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Expand Up @@ -2,7 +2,6 @@

CONFIG_SOC_SERIES_STM32H7X=y
CONFIG_SOC_STM32H745XX=y
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000

# Board config should be specified since there are 2 possible targets
CONFIG_BOARD_NUCLEO_H745ZI_Q_M7=y
Expand All @@ -26,20 +25,5 @@ CONFIG_PINMUX=y
# Enable GPIO
CONFIG_GPIO=y

# Clock Configuration
# Enable Clock
CONFIG_CLOCK_CONTROL=y

# STLINK provides 8MHz clock input
CONFIG_CLOCK_STM32_HSE_CLOCK=8000000
CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL=y

# Use HSE (bypass) as PLL input
CONFIG_CLOCK_STM32_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32_HSE_BYPASS=y

# Produce 480MHz clock at PLL1 output
CONFIG_CLOCK_STM32_PLL_M_DIVISOR=1
CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER=120
CONFIG_CLOCK_STM32_PLL_P_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_Q_DIVISOR=2
CONFIG_CLOCK_STM32_PLL_R_DIVISOR=2