interrupt_controller: intc_esp32c3: added intc driver #38372
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uLipe
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uLipe
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The following west manifest projects have been modified in this Pull Request:
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glaubermaroto
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Hi folks, any considerations there? |
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We are in the stabilization period for v2.7.0 atm, so if the PR does not fix a bug it will not be merged for 2.7.0 unless it has TSC approval. @uLipe - are there many other additions required for supporting the esp32c3 devkit? |
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@cfriedt , for the initial devkitm support is there the WIFI support which is internal tests which may not arrive in the next days. |
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I have a couple of those boards on the way, so I'm looking forward to trying them out :-) |
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@uLipe - please rebase and resolve conflicts |
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September 30, 2021 02:25
For esp32c3 and replaces the hardcoded interrupt attaching procedures with this new driver. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
interrupt controller, also places its relevant peripheral sources allowing drivers to use the DT macros instead of espressif headers. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
Allowing cleaner debug experience and preventing unwanted outputs during debug. Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
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Hi folks, can we move on with this PR? |
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For esp32c3 and replaces the hardcoded interrupt
attaching procedures with this new driver.
The allocation strategy reuses the common riscv software isr table infrastructure provided
by zephyr:
It multiplexes each IRQ with 2 interrupt sources, special cases may have more or less IRQ lines
attached to different sources;
After an IRQ is selected, it is routed to the interrupt matrix as usual and the IRQ is enabled if it was not previously;
The ISR + argument is installed directly into zephyr´s software ISR table entry, the peripheral source number is used directly as table index;
When an ISR occurs, the zephyr platform specific __soc_handle_irq was modified and it is called, and instead of returning the mcause in a0, it returns the source of the peripheral in a0, and this value is used to fetch the proper ISR entry from sw ISR table;
If further interrupts are pending the irq wrapper calls __soc_handle_irq, and from lowest to highest source number, one by one gets checked and placed in a0 for next ISR handle until all pending interrupts get addressed;
When a peripheral source is not needed to interrupt anymore, it is just routed to an inactive IRQ line which is kept permanently disabled preventing it to fire, IRQ line 31 is used by this purpose.