Add support for Cortex-r52

arch/arm/core/aarch32/cortex_a_r/Kconfig

@@ -87,6 +87,13 @@ config CPU_CORTEX_R7
 	help
 	  This option signifies the use of a Cortex-R7 CPU
 
+config CPU_CORTEX_R52
+	bool
+	select CPU_AARCH32_CORTEX_R
+	select AARCH32_ARMV8_R
+	help
+	  This option signifies the use of a Cortex-R52 CPU
+
 if CPU_AARCH32_CORTEX_R
 
 config ARMV7_R
@@ -111,6 +118,19 @@ config ARMV7_R_FP
 	  This option signifies the use of an ARMv7-R processor
 	  implementation supporting the Floating-Point Extension.
 
+config AARCH32_ARMV8_R
+	bool
+	select ATOMIC_OPERATIONS_BUILTIN
+	help
+	  This option signifies the use of an ARMv8-R AArch32 processor
+	  implementation.
+
+	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
+	  The Armv8-R architecture targets at the Real-time profile. It introduces
+	  virtualization at the highest security level while retaining the
+	  Protected Memory System Architecture (PMSA) based on a Memory Protection
+	  Unit (MPU). It supports the A32 and T32 instruction sets.
+
 config ARMV7_EXCEPTION_STACK_SIZE
 	int "Undefined Instruction and Abort stack size (in bytes)"
 	default 256

arch/arm/core/aarch32/cortex_a_r/reset.S

@@ -46,7 +46,40 @@ GTEXT(z_arm_platform_init)
  */
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, z_arm_reset)
 SECTION_SUBSEC_FUNC(TEXT, _reset_section, __start)
+#if defined(CONFIG_AARCH32_ARMV8_R)
+    /* Check if we are starting in HYP mode */
+    mrs r0, cpsr
+    and r0, r0, #MODE_MASK
+    cmp r0, #MODE_HYP
+    bne EL1_Reset_Handler
+
+    /* Init HSCTLR see Armv8-R AArch32 architecture profile */
+    ldr r0, =(HSCTLR_RES1 | SCTLR_I_BIT | SCTLR_C_BIT)
+    mcr p15, 4, r0, c1, c0, 0
+
+    /* Init HACTLR: Enable EL1 access to all IMP DEF registers */
+    ldr r0, =HACTLR_INIT
+    mcr p15, 4, r0, c1, c0, 1
+
+    /* Change EL1 exception base address */
+    ldr r0,=_vector_table
+    mcr p15, 0, r0, c12, c0, 0 /* Write to VBAR */
+
+    /* Go to SVC mode */
+    mrs r0, cpsr
+    mov r1, #MODE_SVC
+    bfi r0, r1, #0, #5
+
+    msr spsr_hyp, r0
+    ldr r0, =EL1_Reset_Handler
+    msr elr_hyp, r0
+    dsb
+    isb
+    eret
+
+EL1_Reset_Handler:
 
+#endif
 #if defined(CONFIG_CPU_HAS_DCLS)
     /*
      * Initialise CPU registers to a defined state if the processor is

arch/arm/core/aarch32/cpu_idle.S

@@ -134,6 +134,7 @@ SECTION_FUNC(TEXT, arch_cpu_atomic_idle)
 
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	/* No BASEPRI, call wfe directly
 	 * (SEVONPEND is set in z_arm_cpu_idle_init())

arch/arm/core/aarch32/isr_wrapper.S

@@ -163,7 +163,8 @@ _idle_state_cleared:
 		/* clear kernel idle state */
 		strne	r1, [r2, #_kernel_offset_to_idle]
 		blne	z_pm_save_idle_exit
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	beq _idle_state_cleared
 	movs r1, #0
 	/* clear kernel idle state */
@@ -252,7 +253,8 @@ spurious_continue:
 	mov lr, r3
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	pop {r0, lr}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	/*
 	 * r0 and lr_irq were saved on the process stack since a swap could
 	 * happen.  exc_exit will handle getting those values back

arch/arm/core/aarch32/swap_helper.S

@@ -120,7 +120,8 @@ out_fp_endif:
      * regardless of whether the thread has an active FP context.
      */
 #endif /* CONFIG_FPU_SHARING */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /* Store rest of process context */
     cps #MODE_SYS
     stm r0, {r4-r11, sp}
@@ -136,7 +137,8 @@ out_fp_endif:
     movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
     msr BASEPRI_MAX, r0
     isb /* Make the effect of disabling interrupts be realized immediately */
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
     /*
      * Interrupts are still disabled from arch_swap so empty clause
      * here to avoid the preprocessor error below
@@ -344,7 +346,8 @@ in_fp_endif:
     /* load callee-saved + psp from thread */
     add r0, r2, #_thread_offset_to_callee_saved
     ldmia r0, {v1-v8, ip}
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 _thread_irq_disabled:
     /* load _kernel into r1 and current k_thread into r2 */
     ldr r1, =_kernel
@@ -602,7 +605,8 @@ valid_syscall_id:
     bx lr
 #endif /* CONFIG_USERSPACE */
 
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 
 /**
  *

arch/arm/core/aarch32/thread.c

@@ -563,6 +563,7 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	"movs r1, #0\n\t"
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) \
 	|| defined(CONFIG_ARMV7_R) \
+	|| defined(CONFIG_AARCH32_ARMV8_R) \
 	|| defined(CONFIG_ARMV7_A)
 	"cpsie i\n\t"		/* __enable_irq() */
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)

cmake/gcc-m-cpu.cmake

@@ -40,6 +40,8 @@ if("${ARCH}" STREQUAL "arm")
     set(GCC_M_CPU cortex-r5)
   elseif(CONFIG_CPU_CORTEX_R7)
     set(GCC_M_CPU cortex-r7)
+  elseif(CONFIG_CPU_CORTEX_R52)
+    set(GCC_M_CPU cortex-r52)
   elseif(CONFIG_CPU_CORTEX_A9)
     set(GCC_M_CPU cortex-a9)
   else()

drivers/interrupt_controller/intc_gicv3.c

@@ -235,8 +235,12 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
 	/* Extract affinity fields from target */
 	aff1 = MPIDR_AFFLVL(target_aff, 1);
 	aff2 = MPIDR_AFFLVL(target_aff, 2);
+#if defined(CONFIG_ARM)
+	/* There is no Aff3 in AArch32 MPIDR */
+	aff3 = 0;
+#else
 	aff3 = MPIDR_AFFLVL(target_aff, 3);
-
+#endif
 	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
 				   SGIR_IRM_TO_AFF, target_list);
 

dts/bindings/cpu/arm,cortex-r52.yaml

@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This is a representation of ARM Cortex-R52 CPU.
+
+compatible: "arm,cortex-r52"
+
+include: cpu.yaml

include/arch/arch_inlines.h

@@ -14,6 +14,8 @@
 
 #if defined(CONFIG_X86) || defined(CONFIG_X86_64)
 #include <arch/x86/arch_inlines.h>
+#elif defined(CONFIG_ARM)
+#include <arch/arm/aarch32/arch_inlines.h>
 #elif defined(CONFIG_ARM64)
 #include <arch/arm64/arch_inlines.h>
 #elif defined(CONFIG_ARC)

include/arch/arm/aarch32/arch.h

@@ -40,8 +40,13 @@
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
 #include <arch/arm/aarch32/cortex_a_r/cpu.h>
 #include <arch/arm/aarch32/cortex_a_r/sys_io.h>
+#if defined(CONFIG_AARCH32_ARMV8_R)
+#include <arch/arm/aarch32/cortex_a_r/lib_helpers.h>
+#include <arch/arm/aarch32/cortex_a_r/armv8_timer.h>
+#else
 #include <arch/arm/aarch32/cortex_a_r/timer.h>
 #endif
+#endif
 
 #ifdef __cplusplus
 extern "C" {

include/arch/arm/aarch32/arch_inlines.h

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2022 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_INLINES_H
+#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_INLINES_H
+
+#include <kernel_structs.h>
+
+#ifndef CONFIG_SMP
+static ALWAYS_INLINE _cpu_t *arch_curr_cpu(void)
+{
+	/* Dummy implementation always return the first cpu */
+	return &_kernel.cpus[0];
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ARCH_INLINES_H */

include/arch/arm/aarch32/asm_inline_gcc.h

@@ -61,7 +61,8 @@ static ALWAYS_INLINE unsigned int arch_irq_lock(void)
 		: "=r"(key), "=r"(tmp)
 		: "i"(_EXC_IRQ_DEFAULT_PRIO)
 		: "memory");
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	__asm__ volatile(
 		"mrs %0, cpsr;"
 		"and %0, #" TOSTR(I_BIT) ";"
@@ -96,7 +97,8 @@ static ALWAYS_INLINE void arch_irq_unlock(unsigned int key)
 		"msr BASEPRI, %0;"
 		"isb;"
 		:  : "r"(key) : "memory");
-#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_ARMV7_A)
+#elif defined(CONFIG_ARMV7_R) || defined(CONFIG_AARCH32_ARMV8_R) \
+	|| defined(CONFIG_ARMV7_A)
 	if (key != 0U) {
 		return;
 	}

include/arch/arm/aarch32/cortex_a_r/armv8_timer.h

@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ * Copyright (c) 2022 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <drivers/timer/arm_arch_timer.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ARM_ARCH_TIMER_IRQ	ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO	ARM_TIMER_VIRTUAL_PRIO
+#define ARM_ARCH_TIMER_FLAGS	ARM_TIMER_VIRTUAL_FLAGS
+
+static ALWAYS_INLINE void arm_arch_timer_init(void)
+{
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
+{
+	write_cntv_cval(val);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
+{
+	uint64_t cntv_ctl;
+
+	cntv_ctl = read_cntv_ctl();
+
+	if (enable) {
+		cntv_ctl |= CNTV_CTL_ENABLE_BIT;
+	} else {
+		cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
+	}
+
+	write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
+{
+	uint64_t cntv_ctl;
+
+	cntv_ctl = read_cntv_ctl();
+
+	if (mask) {
+		cntv_ctl |= CNTV_CTL_IMASK_BIT;
+	} else {
+		cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
+	}
+
+	write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
+{
+	return read_cntvct();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_ */

include/arch/arm/aarch32/cortex_a_r/cmsis.h

@@ -46,6 +46,8 @@ extern "C" {
 #include <core_cr5.h>
 #elif defined(CONFIG_CPU_CORTEX_R7)
 #include <core_cr7.h>
+#elif defined(CONFIG_CPU_CORTEX_R52)
+#include <core_cr52.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
 /*
  * Any defines relevant for the proper inclusion of CMSIS' Cortex-A