Add support for Cortex-r52 #42220

julien-massot · 2022-01-27T09:49:01Z

This PR introduces ARMv8-R AArch32 profile and adds support for the Cortex-R52.

Cortex-R52 processor is a mid-performance for use in automotive and industrial applications.

This PR adds definition for Cortex R52 and AArch32 ARMv8r, defines cp15 registers access
based on what is done on AArch64 (lib_helpers) that allows to reuse GICv3 driver and arm64 timer driver.

This Cortex-R52 support has been firstly tested with the FVP platforms then on Renesas V3U SoC.

manuargue · 2022-02-13T17:45:37Z

Hello @julien-massot, thanks for this draft. Are you planning to continue the work started on this draft and make a pr? I'm interested on Cortex-R52 support.

julien-massot · 2022-02-14T08:43:33Z

Hello @julien-massot, thanks for this draft. Are you planning to continue the work started on this draft and make a pr? I'm interested on Cortex-R52 support.

Yes thats the plan, this draft is functionnal so that you can use it and have the Gic v3 and arm arch timer working, but open many questions regarding integration.

So I'm waiting for potential inputs on the right direction to take and will submit a PR. This is a requirement to support Renesas R-Car Gen4.
@povergoing @bbolen @carlocaione

include/arch/arm/aarch32/lib_helpers.h

include/arch/arm/aarch32/arch.h

arch/arm/core/aarch32/cortex_a_r/reset.S

arch/arm/core/aarch32/cortex_a_r/Kconfig

include/arch/arm/aarch32/arch_inlines.h

arch/arm/core/aarch32/cortex_a_r/Kconfig

carlocaione · 2022-02-14T09:35:35Z

@julien-massot this is good enough to be moved to PR. Devs usually do not take a look at drafts.

microbuilder · 2022-02-23T01:33:06Z

Just as a FYI, this will require an update once #43040 is merged.

arch/arm/core/aarch32/cortex_a_r/Kconfig

Cortex-R52 is an ARMv8-R processor with AArch32 profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

The ARMv8-R processors always boot into Hyp mode (EL2) To enter EL1: Program the HACTLR register because it defaults to only allowing EL2 accesses. HACTLR controls whether EL1 can access memory region registers and CPUACTLR. Program the SPSR before entering EL1. Other registers default to allowing accesses at EL1 from reset. Set VBAR to the correct location for the vector table. Set ELR to point to the entry point of the EL1 code and call ERET. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

lib_helpers makes easier to access cp15 based registers, it is inspired from arm64 lib_helpers but use MRC instead of MRS and use cp15 register. Definitions on how to access system registers for AArch32 Armv8 processors can be found in the document: Arm Architecture Reference Manual Armv8, for Armv8-A architecture profile Signed-off-by: Julien Massot <julien.massot@iot.bzh>

This is mostly a copy of the existing arm64 implementation, at the difference that the AArch32 registers do not mention the execution level. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

These definitions are required to be able to use GICv3 interrupts controller on an ARMv8 AArch32 processor. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

This is required by drivers which query the current cpu, at this moment there is no arm aarch32 that use smp, so it seems safe to consider that the current cpu is always the first one. This patch enable the use of the GICv3 driver on ARM 32bits cpu. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

julien-massot · 2022-03-08T09:49:48Z

@carlocaione @povergoing @microbuilder Any comments on this PR ?

povergoing

LGTM :)

aaillet

As Julien said, we tested this patchset internally for some time now on Renesas V3U SoC CR52 core.
We are able to run all basic Zephyr samples and every basic features seems to work fine.
Thanks Julien.

microbuilder · 2022-03-08T10:36:41Z

@julien-massot How can I test this? There's no QEMU support available for the Cortex-r52, and I don't see a board in upstream Zephyr that I can do a build test with (please correct me if I'm wrong)?

julien-massot · 2022-03-08T10:50:59Z

@microbuilder
Indeed there is no board support. We(IoT.bzh) are waiting for this PR to send initial support for Renesas Gen4. We used to test this port with FVP platforms but since I no longer have a valid license I'm not able to provide a board support.
I think that introducing Renesas Gen4 with this PR will make it to big.

In order to do build/run testing I'm using this branch
https://github.com/iotbzh/zephyr/tree/r52-falcon
It includes this PR and add board and SoC definition for Renesas Falcon board (V3U)
'rcar_falcon_cr52'.

ayankuma · 2022-03-08T16:33:32Z

@julien-massot I was going to ask the same question about testing, but then I saw your response above.

About FVP, I am using https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms and I think they are free of charge.
Actually, I used this port with these changes suggested by @povergoing :-

diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c
index 2c5372f6b8..4f5c55b9ed 100644
--- a/arch/arm64/core/reset.c
+++ b/arch/arm64/core/reset.c
@@ -129,7 +129,6 @@ void z_arm64_el2_init(void)
 
        zero_cntvoff_el2();             /* Set 64-bit virtual timer offset to 0 */
        zero_cnthctl_el2();
-       zero_cnthp_ctl_el2();
        /*
         * Enable this if/when we use the hypervisor timer.
         * write_cnthp_cval_el2(~(uint64_t)0);
diff --git a/boards/arm64/fvp_baser_aemv8r/board.cmake b/boards/arm64/fvp_baser_aemv8r/board.cmake
index fe524007c9..02f72eceb2 100644
--- a/boards/arm64/fvp_baser_aemv8r/board.cmake
+++ b/boards/arm64/fvp_baser_aemv8r/board.cmake
@@ -5,7 +5,7 @@ set(SUPPORTED_EMU_PLATFORMS armfvp)
 set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
 
 set(ARMFVP_FLAGS
-  -C cluster0.has_aarch64=1
+  -C cluster0.has_aarch64=0
   -C cluster0.VMSA_supported=0
   -C cluster0.NUM_CORES=${CONFIG_MP_NUM_CPUS}
   -C cluster0.gicv3.cpuintf-mmap-access-level=2

I built (west build -b fvp_baser_aemv8r samples/synchronization). And then I execute this :-

ayankuma@xcbayankuma41x:/scratch/ayankuma/zephyr/zephyrproject/zephyr$ west build -t run
WARNING: ZEPHYR_BASE= in the calling environment will be used,
but the zephyr.base config option in /scratch/ayankuma/zephyr/zephyrproject is "zephyr"
which implies a different ZEPHYR_BASE=/scratch/ayankuma/zephyr/zephyrproject/zephyr
To disable this warning in the future, execute 'west config --global zephyr.base-prefer env'
-- west build: running target run
[0/1] FVP: /scratch/ayankuma/fastmodel/AEMv8R_base_pkg/models/Linux64_GCC-6.4/FVP_BaseR_AEMv8R
terminal_0: Listening for serial connection on port 5000
terminal_1: Listening for serial connection on port 5001
terminal_2: Listening for serial connection on port 5002
terminal_3: Listening for serial connection on port 5003
^C

I do not get any prints. Please let me know what I am missing. My aim is to build and run an application for Cortex R52 FVP.

microbuilder · 2022-03-08T17:03:37Z

It's hard to approve without providing something to at least do build tests against, but Zephyr actually has support for using FVP for emulation already.

See, for example:

Cortex-M55: MPS3_AN547 where we need the FVP image for Ethos-U55 support: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm/mps3_an547/board.cmake
Cortex R: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_baser_aemv8r/board.cmake
Cortex A: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_base_revc_2xaemv8a/board.cmake

Some FVP images are free, such as the MPS3 AN547 (Corestone 300), but the Cortex-R52 FVP does indeed require a license.

Did you put together a BSP for the R52 FVP already? If so, could that be provided in a separate PR? I believe there are evaluation licenses, but the FVP is something I could probably get a license for to test, at least, and may be useful for CI.

povergoing · 2022-03-09T02:33:33Z

@julien-massot I was going to ask the same question about testing, but then I saw your response above.

About FVP, I am using https://developer.arm.com/tools-and-software/simulation-models/fixed-virtual-platforms and I think they are free of charge. Actually, I used this port with these changes suggested by @povergoing :-
diff --git a/arch/arm64/core/reset.c b/arch/arm64/core/reset.c
index 2c5372f6b8..4f5c55b9ed 100644
--- a/arch/arm64/core/reset.c
+++ b/arch/arm64/core/reset.c
@@ -129,7 +129,6 @@ void z_arm64_el2_init(void)
 
        zero_cntvoff_el2();             /* Set 64-bit virtual timer offset to 0 */
        zero_cnthctl_el2();
-       zero_cnthp_ctl_el2();
        /*
         * Enable this if/when we use the hypervisor timer.
         * write_cnthp_cval_el2(~(uint64_t)0);
diff --git a/boards/arm64/fvp_baser_aemv8r/board.cmake b/boards/arm64/fvp_baser_aemv8r/board.cmake
index fe524007c9..02f72eceb2 100644
--- a/boards/arm64/fvp_baser_aemv8r/board.cmake
+++ b/boards/arm64/fvp_baser_aemv8r/board.cmake
@@ -5,7 +5,7 @@ set(SUPPORTED_EMU_PLATFORMS armfvp)
 set(ARMFVP_BIN_NAME FVP_BaseR_AEMv8R)
 
 set(ARMFVP_FLAGS
-  -C cluster0.has_aarch64=1
+  -C cluster0.has_aarch64=0
   -C cluster0.VMSA_supported=0
   -C cluster0.NUM_CORES=${CONFIG_MP_NUM_CPUS}
   -C cluster0.gicv3.cpuintf-mmap-access-level=2
I built (west build -b fvp_baser_aemv8r samples/synchronization). And then I execute this :-

ayankuma@xcbayankuma41x:/scratch/ayankuma/zephyr/zephyrproject/zephyr$ west build -t run WARNING: ZEPHYR_BASE= in the calling environment will be used, but the zephyr.base config option in /scratch/ayankuma/zephyr/zephyrproject is "zephyr" which implies a different ZEPHYR_BASE=/scratch/ayankuma/zephyr/zephyrproject/zephyr To disable this warning in the future, execute 'west config --global zephyr.base-prefer env' -- west build: running target run [0/1] FVP: /scratch/ayankuma/fastmodel/AEMv8R_base_pkg/models/Linux64_GCC-6.4/FVP_BaseR_AEMv8R terminal_0: Listening for serial connection on port 5000 terminal_1: Listening for serial connection on port 5001 terminal_2: Listening for serial connection on port 5002 terminal_3: Listening for serial connection on port 5003 ^C

I do not get any prints. Please let me know what I am missing. My aim is to build and run an application for Cortex R52 FVP.

No, It surely does not work. As I said, this PR may be the initial support of R52, you cannot use fvp_baser_aemv8r board without any change. fvp_baser_aemv8r is based on AArch64 (ARM64)

povergoing · 2022-03-09T02:42:23Z

It's hard to approve without providing something to at least do build tests against, but Zephyr actually has support for using FVP for emulation already.

See, for example:

Cortex-M55: MPS3_AN547 where we need the FVP image for Ethos-U55 support: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm/mps3_an547/board.cmake

Cortex R: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_baser_aemv8r/board.cmake

Actually, FVP_BaseR_AEMv8R used by (Cortex R: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_baser_aemv8r/board.cmake) can also run in AArch32 mode (-C cluster0.has_aarch64=0) so that this fvp can be simulated almost the same as R52. @julien-massot you can use FVP_BaseR_AEMv8R as the R52 to run Zephyr.

Cortex A: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_base_revc_2xaemv8a/board.cmake

Some FVP images are free, such as the MPS3 AN547 (Corestone 300), but the Cortex-R52 FVP does indeed require a license.

Did you put together a BSP for the R52 FVP already? If so, could that be provided in a separate PR? I believe there are evaluation licenses, but the FVP is something I could probably get a license for to test, at least, and may be useful for CI.

It's better to provide something to do build tests

julien-massot · 2022-03-09T08:40:40Z

Actually, FVP_BaseR_AEMv8R used by (Cortex R: https://github.com/zephyrproject-rtos/zephyr/blob/main/boards/arm64/fvp_baser_aemv8r/board.cmake) can also run in AArch32 mode (-C cluster0.has_aarch64=0) so that this fvp can be simulated almost the same as R52. @julien-massot you can use FVP_BaseR_AEMv8R as the R52 to run Zephyr.

Thank you so much @povergoing, looks like we have something to test this support !

-- Build files have been written to: /home/julien/src/zephyr-new/fvp32-hello
[31/40] Linking C executable zephyr/zephyr_pre0.elf

[34/40] Linking C executable zephyr/zephyr_pre1.elf

[39/40] Linking C executable zephyr/zephyr.elf
Memory region Used Size Region Size %age Used
FLASH: 0 GB 64 MB 0.00%
SRAM: 17612 B 2 MB 0.84%
IDT_LIST: 0 GB 2 KB 0.00%
[39/40] FVP: /home/julien/dev/FVP_Base_AEMv8R_11.17_21/AEMv8R_base_pkg/models/Linux64_GCC-9.3/FVP_BaseR_AEMv8R
terminal_0: Listening for serial connection on port 5000
terminal_1: Listening for serial connection on port 5001
terminal_2: Listening for serial connection on port 5002
terminal_3: Listening for serial connection on port 5003
*** Booting Zephyr OS build zephyr-v3.0.0-649-gde909461f6a0 ***
Hello World! fvp_baser_aemv8r_aarch32

carlocaione · 2022-03-09T09:01:48Z

Thank you so much @povergoing, looks like we have something to test this support !

In that case please add a new FVP board for this.

julien-massot · 2022-03-10T15:04:55Z

superseded by #43581 which also bring FVP platform.

julien-massot requested review from bbolen, carlescufi, galak, ioannisg, MaureenHelm, nashif, stephanosio and tejlmand as code owners January 27, 2022 09:49

github-actions bot added area: API Changes to public APIs area: ARM ARM (32-bit) Architecture area: Build System area: Devicetree area: Devicetree Binding PR modifies or adds a Device Tree binding labels Jan 27, 2022

julien-massot changed the title ~~Add support for Cortex-r52~~ DRAFT: Add support for Cortex-r52 Jan 27, 2022

julien-massot marked this pull request as draft January 27, 2022 09:50

julien-massot force-pushed the iotbzh/Cortex-R52 branch 2 times, most recently from 10f1d34 to d3786a4 Compare January 27, 2022 14:04

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Julien Massot added 6 commits March 2, 2022 13:29

arch: arm: Add support for Cortex-R52

4fc8e5a

Cortex-R52 is an ARMv8-R processor with AArch32 profile. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

arch: arm: aarch32: add ARMv8 timer

61e670e

This is mostly a copy of the existing arm64 implementation, at the difference that the AArch32 registers do not mention the execution level. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

arch: arm: cortex_a_r: add MPIDR and SG1R definition

fba0cc0

These definitions are required to be able to use GICv3 interrupts controller on an ARMv8 AArch32 processor. Signed-off-by: Julien Massot <julien.massot@iot.bzh>

julien-massot force-pushed the iotbzh/Cortex-R52 branch from 9802a2f to 1c4d5f9 Compare March 2, 2022 12:29

povergoing previously approved these changes Mar 8, 2022

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julien-massot mentioned this pull request Mar 9, 2022

Add support for ARMv8-R AArch32 FVP platform #43581

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Add support for Cortex-r52 #42220

Add support for Cortex-r52 #42220

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Add support for Cortex-r52 #42220

Add support for Cortex-r52 #42220

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