boards: heltec_wifi_lora32_v2: enable lora

[gportay]

Dear Maintainers,

This PR enables and defines the lora node (Semtech SX1276) connected through the SPI, including the first three DIO PINs.

One can compile and test LoRa on an Heltec WiFi LoRa32 V2 board.

For example:

First build:

$ west build -p -b heltec_wifi_lora32_v2 zephyr/samples/subsys/shell/shell_module/ -- -DSHIELD=ssd1306_128x64

Then, enable CONFIG_SPI, CONFIG_LORA, CONFIG_LORA_SX127X via the menuconfig:

$ west build -t menuconfig

Finally, flash and run:

$ west flash && picocom -b 115200 /dev/ttUSB0
(...)
uart:~$ lora config freq 868000000

On first board:

$ lora config freq 868000000
uart:~$ lora recv
00000000: 68 65 6c 6c 6f                                   |hello            |
RSSI: -133 dBm, SNR:-13 dBm

On second board:

$ lora config freq 868000000
uart:~$ lora send hello

Regards,
Gaël

---

This enables the support for the Semtech SX1276 chip on board (see the pinout1 and schematic2 documents).

The chip is connected to SPI as follow:

PIN	GPIO
CS#	GPIO18
CLK	GPIO5
MOSI	GPIO27
MISO	GPIO19
RST#	GPIO14

Additionally, the LoRa DIO PINs are connected as follow:

PIN	GPIO
DIO0	GPIO26
DIO1	GPIO35
DIO2	GPIO34

Note: The first three DIO PINs are connected to the ESP32 MCU only.

Signed-off-by: Gaël PORTAY gael.portay@gmail.com

[gportay]

I wanted to stay consistent across other ESP32 boards by defining the pinmux node the same way, i.e. including the CS# PIN.

But adding the SPIM3_CSEL_GPIO18 to the group breaks the SPI communication and I do not know why.

Maybe someone can explain me what is wrong?

However, I guess it makes sens to leave it undefined. It is setup via the cs-gpio from the spi3 node.

Also, all the PINs are connected directly from the ESP32 to the SX1276 without any pull-up or pull-down (according to the schematics).

Can someone explain to me if I should add output-low or up or bias-pull-down or up?

Thanks

[gportay]

I would be pleased if someone can give some tips about what I mentioned above to make sure this is the right solution. Thanks.

[sylvioalves]

@gportay Hi,
However, I guess it makes sens to leave it undefined. It is setup via the cs-gpio from the spi3 node.
Regarding the CS pin, you are correct, it is already there in cs-gpio.

You can keep output-low; in the MOSI pins as well. It sets this pin as output with low level.

About the gpio/dio connected between ESP32 and SX1762, the SX1762 datasheet does not mention that a pull-up is required in those pins, so it seems you are good as is.

[sylvioalves]

Seems good. I don't have a board to test it though.