Add support for Intel FPGA Nios V/g General Purpose Processor #59043
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zephyrbot
requested review from
carlocaione,
edersondisouza,
fkokosinski,
katsuster,
mgielda and
tgorochowik
| To download the Zephyr Executable and Linkable Format .elf file, please use the niosv-download command within Nios V Command Shell environment. | ||
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| .. code-block:: console | ||
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| niosv-download -g <elf file> |
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a west runner should be implemented
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Okay. But suggest to have separate PR to support this.
I will study how west runner can works without niosv-download utility and can submit separate PR once it works for niosv_g and also niosv_m.
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sure, it's ok, just noting to avoid adding more boards with custom flashing mechanisms. I think we should be consistent and offer a uniform user experience.
| CONFIG_PRINTK=y | ||
| CONFIG_SERIAL=y | ||
| CONFIG_UART_CONSOLE=y | ||
| CONFIG_UART_ALTERA_JTAG=y |
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Got it, will remove this. Thanks.
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This needs rebasing after 8eeb5c9. |
Rebase done. Thanks. |
sweeaun
dismissed stale reviews from henrikbrixandersen and carlocaione
via
723f372
Add support for INTEL FPGA Nios V/g RISC-V based Processors. Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Add basic dts support for INTEL Nios V/g General Purpose Processor. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Add board support for INTEL Nios V/g General Processor. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
Add code owner for INTEL FPGA Nios V/g dts, SoC and board. Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
| reg = <0>; | ||
| clock-frequency = <50000000>; | ||
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| /* Platform interrupts IRQs index start from 16 */ |
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Uhm, are you in this exact situation then? #59035
How are you dealing with this offset?
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@carlocaione , I have to add the offset manual in device tree. Nice patch from you to enable this, hope it go in main line soon.
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@carlocaione, wonder will that patch add offset to riscv machine timer as well? I don't think machine timer need add offset.
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@sweeaun yeah, that is not going to work with this patch then. In my use-case the offset-ted lines are not practically usable anymore. What is your actual configuration? You have CLINT + CLIC?
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Yes. we do hart local interrupt and Platform-Level Interrupt Controller (PLIC).
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oh ok, you have CLINT + PLIC. In that case I think that you can use CONFIG_2ND_LEVEL_INTERRUPTS to get rid of the 16 lines offset.
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Hi @carlocaione , our core doesn't have multiple level and only 1 level for all interrupts. Just that the interrupt 16 to 31 is named as platform interrupt which is not another level of interrupt controller. Sorry for confusion.
https://www.intel.com/content/www/us/en/docs/programmable/683632/23-1/interrupt-controller-91908.html
bit 3 is for software interrupt
bit 7 is for machine timer
bit[31:16] for platform interrupt
I don't think multi level interrupt configuration is needed in our case.
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interesting. Out of curiosity: how the platform is managing mcause? For example mcause for software interrupt is carrying the id 3 and 19 for the third platform interrupt?
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software interrupt registered to irq 3
machine timer registred to irq 7
1st platform interrupt registered to irq 16
2nd platform interrupt registered to irq 17
3rd platform interrupt registered to irq 18
and so on...
In this system, we have jtag-uart connected to 1st platform interrupt. Thus the irq number is 16.
Not sure am I answered your question.
This PR add support for Intel FPGA Nios V/g SoC and board, board system design is based on Intel FPGA Design Store Nios® V/g Hello World Example Design system.
More information about Intel FPGA Nios V/g and Hello World Example Design system can be obtained here:
https://www.intel.com/content/www/us/en/products/details/fpga/nios-processor/v.html
https://www.intel.com/content/www/us/en/design-example/776196/intel-arria-10-fpga-hello-world-design-on-nios-v-g-processor.html
For testing, it was verified with following samples:
hello_world
synchronization
philosophers