soc: atmel: sam/sam0: Add platform specific initialization #61005
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This update Kconfig.series files to normalize copyright date order from lower to higher and reorder select entries. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This reorder <board>_defconfig entries in soc/board, internal and driver definitions. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Adjust copyright order by ascending year order. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This replace pre kernel initialization by the platform specific initialization call. The platform specific init will configure at very beginning the clocks, flash wait states and cache. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current platform initialization do not take in consideration cache management for historic reasons. This fixes any miss configuration and allow users to enable/disable caches at board definition. The default value is cache disabled and the below examples are for SAMV71 which have both I/D Cache available: I Cache only: CONFIG_CACHE_MANAGEMENT=y CONFIG_DCACHE=n D Cache only: CONFIG_CACHE_MANAGEMENT=y CONFIG_ICACHE=n I/D Cache disabled: CONFIG_ICACHE=n CONFIG_DCACHE=n I/D Cache Enabled: CONFIG_CACHE_MANAGEMENT=y Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The sam0 CMCC configure Cortex-M cache controller. However, it is not clear how the cache management should be performed. It is nor clear if instructions like SCB_EnableICache can be used. In this case, if cache management should be made only by CMCC it may require a dedicated implementation. Besides above, the CPU_CORTEX_M4 do not define cache by default which can signal a bad configuration in tree since the SOC_SERIES_SAME54 do not define which caches should be available. This force cache controller disable to avoid issues. Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
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pdgendt
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This replace pre kernel initialization by the platform specific initialization call. The platform specific init will configure at very beginning the clocks, flash wait states and cache.
Supersedes #60425