boards: x86: Add support for Intel Alder Lake boards

boards/x86/intel_adl/CMakeLists.txt

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+# Create an EFI image
+if((CONFIG_BOARD_INTEL_ADL_CRB OR CONFIG_BOARD_INTEL_ADL_RVP) AND CONFIG_BUILD_OUTPUT_EFI)
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+  COMMAND ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
+  -c ${CMAKE_C_COMPILER}
+  -o ${CMAKE_OBJCOPY}
+  -i ${ZEPHYR_BASE}/include
+  -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
+  $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+  WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+)
+endif()

boards/x86/intel_adl/Kconfig.board

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+# Copyright (c) 2023 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_ADL_CRB
+	bool "Alder Lake CRB"
+	depends on SOC_ALDER_LAKE
+	select X86_64
+	select HAS_COVERAGE_SUPPORT
+
+config BOARD_INTEL_ADL_RVP
+	bool "Alder Lake RVP"
+	depends on SOC_ALDER_LAKE
+	select X86_64
+	select HAS_COVERAGE_SUPPORT

boards/x86/intel_adl/Kconfig.defconfig

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+# Copyright (c) 2023 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
+
+config BOARD
+	default "intel_adl_crb" if BOARD_INTEL_ADL_CRB
+	default "intel_adl_rvp" if BOARD_INTEL_ADL_RVP
+
+config BUILD_OUTPUT_STRIPPED
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1900000000 if APIC_TSC_DEADLINE_TIMER
+	default 1900000000 if APIC_TIMER_TSC
+	default 19200000
+
+if APIC_TIMER
+config APIC_TIMER_IRQ
+	default 24
+config APIC_TIMER_TSC_M
+	default 3
+config APIC_TIMER_TSC_N
+	default 249
+endif
+
+config ACPI
+	default y
+
+endif # BOARD_INTEL_ADL_CRB || BOARD_INTEL_ADL_RVP
+
+if BOARD_INTEL_ADL_RVP
+
+config UART_NS16550_ACCESS_IOPORT
+	default y if UART_NS16550
+
+endif # BOARD_INTEL_ADL_RVP

boards/x86/intel_adl/board.cmake

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+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)

boards/x86/intel_adl/doc/index.rst

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+.. _intel_adl_crb:
+
+Alder Lake CRB
+##############
+
+Overview
+********
+Alder Lake Reference Board (INTEL_ADL CRB) is an example implementation of a
+compact single board computer with high performance for IoT edge devices.
+
+This board configuration enables kernel support for the `INTEL_ADL`_ board.
+
+Hardware
+********
+
+General information about the board can be found at the `INTEL_ADL`_ website.
+
+Connections and IOs
+===================
+
+Refer to the `INTEL_ADL`_ website for more information.
+
+Programming and Debugging
+*************************
+Use the following procedures for booting an image on a RPL CRB board.
+
+.. contents::
+   :depth: 1
+   :local:
+   :backlinks: top
+
+Build Zephyr application
+========================
+
+#. Build a Zephyr application; for instance, to build the ``hello_world``
+   application on Alder Lake CRB:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: intel_adl_crb
+      :goals: build
+
+   .. note::
+
+      A Zephyr EFI image file named :file:`zephyr.efi` is automatically
+      created in the build directory after the application is built.
+
+Preparing the Boot Device
+=========================
+
+Prepare a USB flash drive to boot the Zephyr application image on
+an Alder Lake CRB board.
+
+#. Format the USB flash drive as FAT32.
+
+   On Windows, open ``File Explorer``, and right-click on the USB flash drive.
+   Select ``Format...``. Make sure in ``File System``, ``FAT32`` is selected.
+   Click on the ``Format`` button and wait for it to finish.
+
+   On Linux, graphical utilities such as ``gparted`` can be used to format
+   the USB flash drive as FAT32. Alternatively, under terminal, find out
+   the corresponding device node for the USB flash drive (for example,
+   ``/dev/sdd``). Execute the following command:
+
+   .. code-block:: console
+
+      $ mkfs.vfat -F 32 <device-node>
+
+   .. important::
+      Make sure the device node is the actual device node for
+      the USB flash drive. Or else you may erase other storage devices
+      on your system, and will render the system unusable afterwards.
+
+#. Copy the Zephyr EFI image file :file:`zephyr/zephyr.efi` to the USB drive.
+
+Booting the Alder Lake CRB Board
+================================
+
+Boot the Alder Lake CRB board to the EFI shell with USB flash drive connected.
+
+#. Insert the prepared boot device (USB flash drive) into the Alder Lake CRB board.
+
+#. Connect the board to the host system using the serial cable and
+   configure your host system to watch for serial data.  See
+   `INTEL_ADL`_ website for more information.
+
+   .. note::
+      On Windows, PuTTY has an option to set up configuration for
+      serial data.  Use a baud rate of 115200.
+
+#. Power on the Alder Lake CRB board.
+
+#. When the following output appears, press :kbd:`F7`:
+
+   .. code-block:: console
+
+      Press <DEL> or <ESC> to enter setup.
+
+#. From the menu that appears, select the menu entry that describes
+   that particular EFI shell.
+
+#. From the EFI shell select Zephyr EFI image to boot.
+
+   .. code-block:: console
+
+      Shell> fs0:zephyr.efi
+
+.. _INTEL_ADL: https://ark.intel.com/content/www/us/en/ark/products/codename/232598/products-formerly-alder-laken.html

boards/x86/intel_adl/intel_adl.dts

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+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#define DT_DRAM_SIZE		DT_SIZE_M(2048)
+
+#include <intel/alder_lake.dtsi>
+
+/ {
+	model = "Alder Lake";
+	compatible = "intel,alder_lake";
+
+	chosen {
+		zephyr,sram = &dram0;
+	};
+
+	aliases {
+		watchdog0 = &tco_wdt;
+	};
+};

boards/x86/intel_adl/intel_adl_crb.dts

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+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "intel_adl.dts"
+
+/ {
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};

boards/x86/intel_adl/intel_adl_crb.yaml

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+identifier: intel_adl_crb
+name: Alder Lake CRB
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 2048
+supported:
+  - watchdog
+testing:
+  timeout_multiplier: 4
+  ignore_tags:
+    - net
+    - bluetooth

boards/x86/intel_adl/intel_adl_crb_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_ALDER_LAKE=y
+CONFIG_BOARD_INTEL_ADL_CRB=y
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_X2APIC=y
+CONFIG_SMP=y
+CONFIG_BUILD_OUTPUT_EFI=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_HEAP_MEM_POOL_SIZE=64000000
+CONFIG_MAIN_STACK_SIZE=320000
+CONFIG_UART_NS16550_PARENT_INIT_LEVEL=y
+CONFIG_SHELL_BACKEND_SERIAL_INIT_PRIORITY=55

boards/x86/intel_adl/intel_adl_rvp.dts

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+/*
+ * Copyright (c) 2023 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "intel_adl.dts"
+
+/ {
+	chosen {
+		zephyr,console = &uart0_legacy;
+		zephyr,shell-uart = &uart0_legacy;
+	};
+};

boards/x86/intel_adl/intel_adl_rvp.yaml

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+identifier: intel_adl_rvp
+name: Alder Lake RVP
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 2048
+supported:
+  - watchdog
+testing:
+  timeout_multiplier: 4
+  ignore_tags:
+    - net
+    - bluetooth

boards/x86/intel_adl/intel_adl_rvp_defconfig

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+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_ALDER_LAKE=y
+CONFIG_BOARD_INTEL_ADL_RVP=y
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_CONSOLE=y
+CONFIG_X2APIC=y
+CONFIG_SMP=y
+CONFIG_BUILD_OUTPUT_EFI=y
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_HEAP_MEM_POOL_SIZE=64000000
+CONFIG_MAIN_STACK_SIZE=320000
+CONFIG_UART_NS16550_PARENT_INIT_LEVEL=y
+CONFIG_SHELL_BACKEND_SERIAL_INIT_PRIORITY=55

dts/bindings/cpu/intel,alder_lake.yaml

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+# Copyright (c) 2023 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Alder Lake CPU
+
+compatible: "intel,alder-lake"
+
+include: cpu.yaml