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e200_opensource
e200_opensource PublicForked from SI-RISCV/e200_opensource
The Ultra-Low Power RISC Core
Verilog
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Cores-SweRV
Cores-SweRV PublicForked from chipsalliance/Cores-VeeR-EH1
SweRV EH1 core
SystemVerilog
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rocket-chip-sifan
rocket-chip-sifan PublicForked from chipsalliance/rocket-chip
Rocket Chip Generator
Scala
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ariane
ariane PublicForked from openhwgroup/cva6
Ariane is a 6-stage RISC-V CPU capable of booting Linux
SystemVerilog
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chipyard
chipyard PublicForked from ucb-bar/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
C
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ariane-wrapper
ariane-wrapper PublicForked from ucb-bar/cva6-wrapper
Wrapper for ETH Ariane Core
Scala
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