What's Changed
- Update build.sc dependencies by @KireinaHoro in #1275
- VerilatorBackend now cache improvement by @Dolu1990 in #1272
- PackedBundle Bug Fix by @dokleina in #1271
- Fix comments for trait BitwiseOp by @g0t00 in #1281
- XSim: better Windows support + add xcix IP import by @oletf in #1246
- AXI and AXI-Stream simulation bus masters by @KireinaHoro in #1288
- driveStream on BusSlaveFactory by @KireinaHoro in #1289
- allow CounterFreeRun to take bitCount by @KireinaHoro in #1292
- add setOutputAsReg by @KireinaHoro in #1293
- scala 2.12 is now the default by @Dolu1990 in #1283
- Composable exp by @Dolu1990 in #1297
- Sim test folder by @Dolu1990 in #1279
New Contributors
- @KireinaHoro made their first contribution in #1275
- @g0t00 made their first contribution in #1281
- @oletf made their first contribution in #1246
Full Changelog: v1.10.0...v1.10.1
Contributors
g0t00, Dolu1990, and 3 other contributors