ghdl
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✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.
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May 9, 2024 - Python
An abstraction library for interfacing EDA tools
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May 9, 2024 - Python
Course Project - Microprocessors - Spring Semester 2022 - Indian Institute of Technology Bombay
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Apr 5, 2024 - VHDL
GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.
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Mar 11, 2024 - C++
Time domain to logarithmic frequency domain converter, as the polyphase FFT do for the linear.
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Mar 11, 2024 - VHDL
Library of reusable VHDL components
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Mar 7, 2024 - VHDL
Trying to verify Verilog/VHDL designs with formal methods and tools
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Mar 7, 2024 - VHDL
Fun project to produce (only) pulses as the MultiSignalGene do, with analogue circuits and FPGA or 74HC logic circuits.
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Feb 19, 2024 - PostScript
Easy and fast VHDL simulation tool, integrating GHDL and GTKWave
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Feb 17, 2024 - PHP
Projekt (animace na maticovém displeji) z předmětu Seminář VHDL (IVH), čtvrtý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2022/2023
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Jan 12, 2024 - VHDL
Repurposing existing HDL tools to help writing better code
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Dec 20, 2023 - Python
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