Repurposing existing HDL tools to help writing better code
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Updated
Dec 20, 2023 - Python
Repurposing existing HDL tools to help writing better code
the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.
Example of Python and PyTest powered workflow for a HDL simulation
Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.
Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation
Practice Codes of SystemVerilog Language
This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
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