Single Cycle MIPS Pipelined Processor using Verilog
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Aug 22, 2021 - Verilog
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pipelined-risc
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5 stages RISC pipelined processor following Harvard architecture.
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Jan 7, 2023 - Verilog
Pipelined Processor which implements RV32i Instruction Set. Also contains pipelined L1 4-way set-associative Instruction Cache, direct-mapped L1 Data Cache, and a 4-way set-associative L2 Victim Cache with a fully-associative 8-entry Victim Buffer. Also has a tournament branch predictor (global and local predictors) and a set-associative BTB.
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Dec 23, 2022 - Verilog
Hardware designs modelled with verilog
cache
verilog
hardware-designs
computer-architecture
floating-point-multiplication
register-file
floating-point-adder
pipelined-risc
logic-unit
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Mar 9, 2021 - Verilog
Designed a Single Cycle 6-stage pipelined Processor which can execute 26 different instructions and implemented it in code in VHDL
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Jul 21, 2023 - HTML
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