The RISC-V Virtual Machine

A Github Action that executes jobs/commands on non-x86 cpu architectures (ARMv6, ARMv7, aarch64, s390x, ppc64le, riscv64) via QEMU

The Adventures of OS

RISC-V Guide. Learn all about the RISC-V computer architecture along with the Development Tools and Operating Systems to develop on RISC-V hardware.

The juice virtual machine was born in 2020, with the goal of realizing the smallest virtual machine of RISC-V that can run the latest kernel mainline. At the beginning of the design, it runs on a platform with only 100 KB of RAM, which does not exceed the number of C99. Three-party dependence.

World Of Warcraft 3.3.5a server

Simple unix-like operating system for education and research purposes

F# RISC-V Instruction Set formal specification

UEFI Shell binary images, generated from EDK2 stable

Evaluation board for AllWinner's RISC-V 64 SoC F133/D1s

UART based embedded shell for embedded systems. Intended to be used for learning, experimenting and diagnostics.

Toy C compiler for x86-64/aarch64/riscv64/wasm

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

A curated list of awesome MangoPi MQ-Pro images, tools and resources

Simple risc-v emulator, able to run linux, written in C.

😎 A curated list of awesome RISC-V implementations

OpenCar riscv emulator written in java openCar 主要完成一款仿真Riscv指令集的软件，目标是提供基础的Rv指令模拟环境，同时支持各芯片方基于openCar扩展指令以实现趋近于芯片功能的仿真环境，为异构的软件生态提供方便的调试观察功能。

The shortest and fastest script to build working cross compilers targeting musl libc

An AXI4 crossbar implementation in SystemVerilog

Instruction set simulator for RISC-V, MIPS and ARM-v6m