Releases · Xilinx/RapidWright

Use new Cell.{LOCKED,PORT_TYPE,isPortCell()} (#977)
Remove some pre-2023.2.2 workarounds (#978)
[RWRoute] Fix logical driver flag setting for DCP write (#979)
Add explicit use case for a Jython script in --help (#980)
[VivadoTools] Add placeDesign() and getWorstSetupSlack() (#975)
[RWRoute] Consider all nets in timing-driven routing (#976)
[DCP] Test Design.writeCheckpoint() when using existing EDIF (#965)
Work around for multi-inverter BEL in DSP58 (#969)
[DesignTools.makeBlackBox()] Fix for #967 (#970)
[RWRoute,PhysNetlistReader] Set logical driver on PIPs (#973)
[SLRCrosserGenerator] Adds North/South parameterizable bus widths; some error checking (#972)
[EDIFTokenizer] Account for byte size of UTF-8 characters correctly (#962)
[VivadoTools] writeBitstream to not delete DCP parent dir (+more) (#955)
[RWRoute] Preserve [A-H]_O node when [A-H]MUX used as static src (#954)
[GlobalSignalRouter] No intra site routing for new static source pins (#953)
[EDIFPropertyValue] Fix getBooleanValue() NPE (#952)
[PhysNetlistReader] Fix checkConstantRoutingAndNetNaming() (#951)
[RWRoute] When removing unused source SPI restore intra-site routing (#949)
[RWRoute] Tidy up createNetWrapperAndConnections() (#950)
Fix EDIFPropertyValue.getBooleanValue() (#948)
[RWRoute] Replace main src with altsrc if main is unused (#945)
[RWRoute] Fix comment Eastern -> Western (#943)
RouterHelper.invertPossibleGndPinsToVccPins() to invert static LUT inputs (#910)
[TestRWRoute] Stop skipping some tests when < 8GB (#941)
Temporary workaround to clear logical net after Net.rename() (#942)
Known failing test for EDIFHierPortInst.getRoutedSitePinInst() (#577)
Known failing test for Tile.getSites() result different to Vivado (#745)
Known failing test for BITSLICE_CONTROL output pin projection (#559)
Add known failing testcase for #756 (#758)
Update RWRouteConfig.java (#940)
[RWRoute] Add --lutRoutethru option (#932)
[RWRoute] Do not pin swap SRL (shift register) cells (#939)
[LUTTools] LUT pin swapping fixes (#938)
Net.rename() to clear logical hier net
Fix regarding issue around bitstream header
Fixes issue when site wire lacks GND tag

API Additions:

com.xilinx.rapidwright.bitstream.Bitstream "public boolean writeBitstream(Path path)"
com.xilinx.rapidwright.bitstream.Frame "public List getDiff(Frame otherFrame)"
com.xilinx.rapidwright.design.Cell "public static final String LOCKED = "";
com.xilinx.rapidwright.design.Cell "public static final String PORT_TYPE = "";
com.xilinx.rapidwright.design.Cell "public boolean isPortCell()"
com.xilinx.rapidwright.design.Cell "public String getPropertyValueString(String key)"
com.xilinx.rapidwright.design.Design "public void writeCheckpoint(String dcpFileName, String edfFileName, CodePerfTracker t)"
com.xilinx.rapidwright.design.Design "public void writeCheckpoint(Path dcpFileName, Path edfFileName, CodePerfTracker t)"
com.xilinx.rapidwright.design.Design "public void detachNetlist(Predicate preserveCellProperties)"
com.xilinx.rapidwright.device.BEL "public static BEL getBEL(Device device, SiteTypeEnum siteTypeEnum, String belName)"
com.xilinx.rapidwright.device.PIP "public boolean isArcInverted()"
com.xilinx.rapidwright.device.PIP "public void setIsLogicalDriver(boolean isLogicalDriver)"
com.xilinx.rapidwright.device.SitePIP "public int getIndex()"
com.xilinx.rapidwright.device.SitePIP "public static SitePIP getSitePIP(Device device, SiteTypeEnum siteTypeEnum, int sitePIPIndex)"

Assets 9

10 Jan 23:33

clavin-xlnx

v2023.2.1-beta

90312fd

RapidWright 2023.2.1-beta Release

Release Notes:

Add EDIFHierCellInst.isUniquified() (#918)
[RWRoute] RouteNode to extend Node (#916)
[DesignComparator] Fix whitespace (#937)
RouteThruHelper.isRouteThruPIPAvailable(Design, WireInterface, WireIn (#915)
Create a common interface for Node and Wire Objects (#892)
DesignComparator - compares place and route data (#931)
DesignTools.createMissingSitePinInsts() to infer SitePinInsts more smartly (#936)
LUTTools.swapLutPinsFromPIPs() to warn when site pin not found (#934)
[PhysNetlistReader] Warn and omit if PIP not found (#933)
[PhysNetlistWriter] Handle PORT cells in GTY tiles (#930)
[PhysNetlistWriter] Assume static net output BELPins to be sources too (#929)
[PhysNetlistWriter] Fix stubs on static nets (#928)
Get a Boolean from EDIFPropertyValue (#926)
[PhysNetlistWriter] Infer direction of IOB's PAD.PAD BEL pin (#927)
[RouteThruHelper] Move assertions, improve tests (#925)
[RWRoute] Don't swap dist RAMs on 'H' BELs since A and WA are shared (#924)
[PhysNetlistWriter] Recognize static source BELPins (e.g. LUT outputs) (#923)
[RWRoute] Analyze a tile below the topmost arbitrary one (#921)
Adding test for IOB placement (#903)
[DesignTools.makeBlackBox()] Fixes routing issues in makeBlackBox() (#919)
[ECOTools] Inline cell insertion (#917)
RouterHelper.invertPossibleGndPinsToVccPins() to work on all invertible pins (#911)
[RWRoute] GlobalSignalRouting static net router to use [A-H]MUX outputs (#914)
[RWRoute] Fix exception for unrouteable connections (#913)
Declare gradle dependency explicitly (#909)
Fixes [Versal BELAttr] Parsing issue #912
Add site pins when site routing through inverter BELs
Fix UltraScale+ IBUF site routing
Fix DSP pin mapping removals during site routing
Adds support for special clock Node flag present in Versal designs

API Additions:

com.xilinx.rapidwright.device.Node "public Node(Node node)"
com.xilinx.rapidwright.device.Package "public synchronized PackagePin getPackagePin(Site site)"
com.xilinx.rapidwright.device.Package "public String getPackagePinName(Site site)"

Assets 9

20 Nov 21:48

clavin-xlnx

v2023.2.0-beta

c4088d2

RapidWright 2023.2.0-beta Release

Release Notes:

SLR Corner updates in device models and handling (#886)
Updates Protobuf to 3.25.0 (#882)
Updates/adds timestamp APIs (#883)
Refactor PROHIBIT constraint for faster Tcl interpretation (#881)
[PerformanceExplorer] Number pblocks by order in file, add first site in dir name (#867)
DesignTools.createMissingSitePinInsts(Design) to ignore GLOBAL_USEDNET (#880)
[RWRoute] Check source & sink pin reaches INT tile for dedicated connections (#878)
ECOTools.createExitSitePinInst() to detect net aliases (#871)
Rewrite RouterHelper.projectOutputPinToINTNode() with fixes (#877)
EDIFNetlist.{generateParentNetMap,getNetAliases}() to be inout-aware (#876)
DesignTools.createMissingSitePinInsts() to cope with net aliases (#875)
Improve TestECOPlacementHelper (#874)
Add com.xilinx.rapidwright.eco.ECOPlacementHelper (#870)
RouteThruHelper to handle SiteInst == null (#866)
Add RouteThruHelper.isRouteThruPIPAvailable(Design, Node, Node) overload (#865)
Add DesignTools.getConnectedBELPins() (#864)
RelocationTools fixes and more robust testing (#863)
Fix TimingAndWirelengthReport.main() (#860)
[Tests] Symlinks to absolute paths (#862)
added check to see if Cell.getLogicalPinMapping() is null (#783)
[DCP] Update tests to infer SitePinInsts (#857)
Replace $(shell ...) with $(wildcard) and $(subst) in Makefile (#856)
Undpreccate Design.createCell()
Special clock flag fix for Versal DCPs
More conservative SitePinInst creation upon DCP load

API Additions:

com.xilinx.rapidwright.design.SitePinInst "public int getConnectedTileWire()"
com.xilinx.rapidwright.device.Device "public int getSiteIndex(String siteName)"
com.xilinx.rapidwright.device.Device "public int getSiteIndex(Site site)"
com.xilinx.rapidwright.device.Device "public Site getSiteByIndex(int siteIndex)"
com.xilinx.rapidwright.device.Device "public Site[] getAllSites()"

API Removals:

com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow()"

Assets 9

20 Oct 17:14

clavin-xlnx

v2023.1.4-beta

4f8ea93

RapidWright 2023.1.4-beta Release

Release Notes:

Include RapidWright API Lib Javadoc in Gradle Build (#855)
Add com.xilinx.rapidwright.eco.ECOTools package (#850)
More Polynomial Generator improvements (#854)
ReportRouteStatusResult.isFullyRouted() to check >0 logical net found (#852)
Fixes for the PolynomialGenerator (tutorial) (#846)
Test that Design.createModuleInst() copies static sources (#839)
ModuleInst.place() to check both RAMB36/RAMB18 sites for overlap (#841)
PartialRouter preprocessing and clock routing improvements (#843)
Updates to Interchange README.md (#832)
Simplify and make DesignTools.updatePinsIsRouted() more robust (#844)
RouterHelper.invertPossibleGndPinsToVccPins() to not invert BRAM CLKs (#840)
ModuleInst.connect() to leave physical Net alone for pass-thrus (#722)
Unroute site routing when removing a cell (#729)
PartialRouter's global router to not unpreserve sink nodes (#736)
DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
Add DcpToInterchange class (#704)
Add compile step (#733)
Add EdifToLogicalNetlist to MainEntrypoint (#731)
[PhysNetlistReader] Set Cell type for routethru cells (#727)
Fix Javadoc warnings (#723)
Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
Multilevel macro expansion (#726)
TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
Add missing Versal DSP SiteTypeEnum (#842)
[RWRoute] Further fix/cleanup around alternate source pins (#830)
Adding out-of-context flag to RWRoute (#836)
fix a bug in PipelineGeneratorWithRouting.createPipeline() (#837)
Fix verb tense in RWRoute INFO msg (#835)
Enable RWRoute to load Interchange designs from main() (#834)
[VivadoTools] Check for Vivado on PATH first (#831)
[EDIFNetlist] - Ensure Macro Expansion Deep Copies Children (#828)
Minor RWRoute and UltraScaleClockRouting fixes (#829)
Properly add/remove dual-output pins (#825)
[TestRouteNode] Update comment; swap east and west (#827)
Add VivadoTools.reportRouteStatus() overload for specific net status (#823)
Update link to Discussions forum (#824)
[RWRoute] Only add alternative sources to SiteInst if used (#821)
RouteNode.getPIPsBackToSource() to recognize reversed PIPs (#822)
[PhysNetlistReader] Create FFRoutethruCell-s correctly (#817)
Add test for Design.movePinsToNewNetDeleteOldNet() (#796)
Test Cell.getAllCorrespondingSitePinNames() works for multi-outputs (#792)
[PhysNetlistWriter] No IO site port output BELPins without SitePinInst (#820)
[PhysNetlistWriter] Set PhysPip.setForward() even if not bidir (#819)
[PhysNetlistWriter] Skip output BELPins without cells, and port cells (#818)
Test that Design.createModuleInst() copies static sources (#839)
Design.createModuleInst() to copy STATIC_SOURCE_ SiteInsts properly
Store partname in netlist for new designs
SiteInst.addPin() to trackChanges() when ?_O or ?MUX pin added
Method parameter names preserved in API lib jar
API Additions:
- com.xilinx.rapidwright.design.Module "public Cell getCell(String cellName)"
- com.xilinx.rapidwright.design.Net "public boolean isVCCNet()"
- com.xilinx.rapidwright.design.Net "public boolean isGNDNet()"
- com.xilinx.rapidwright.design.Net "public boolean isUsedNet()"

Assets 9

14 Sep 02:36

clavin-xlnx

v2023.1.3-beta

7cec512

RapidWright 2023.1.3-beta Release

Release Notes:
Notes:

Fix DesignTools.getConnectionPIPs() (#809)
[PhysNetlistWriter] RouteBranchNode.getDrivers() to return input BelPin (#800)
Adds site pins to example code generation for nets. (#807)
Update to fixed microblazeAndILA_3pblocks.dcp (#808)
[LogNetlistWriter] Refactor writeStrings method to be public static (#804)
[VivadoTools] ReportRouteStatusResult to parse more stats (#805)
EDIF improvements (#806)
RWRoute improvements (#803)
Adds a createBitstream() method to VivadoTools (#801)
Small DesignTools improvements (#797)
added static function that helps produce test nets (including PIPs) (#784)
Add reference copy methods (#794)
[RWRoute] Add alternate source pins and set source routed flags (#787)
Adds support for RouteThru LUT equations and makes LUTEquationEvaluator public (#795)
Fix TestDCPLoad to prevent issues with parallel testing (#793)
[PhysNetlistWriter] Fix route tree construction for bidir PIPs (#791)
VivadoTools.reportRouteStatus() to handle encrypted cells (#777)
[PhysNetlistWriter] Insert site port BELPin before site pin (#790)
fixed null pointer exception in getPhysicalNetFromPin() (#775)
LUT cell companion helper methods (#764)
Check for error situation RAPIDWRIGHT_PATH set but not CLASSPATH (#772)
Set reversed flag on bi-directional PIPs used from end->start (#774)
Fix RouterHelper.projectOutputPinToINTNode() for depop pins (#779)
Make PartialRouter.getUnroutedPins() public (#778)
FileTools.runCommand() - Adds ability to choose run directory (#769)
[GlobalSignalRouting] Static router to not create site pin if exists (#768)
RouteThru support for FFs in UltraScale architecture
Fixes minor SitePinInst creation when reading a DCP
Improvements to Net.rename() when tracking changes
Design.detachNetlist() to detach routethru cells
Adds reference copy APIs and ability to keep copies of modified
SiteInsts and Nets
Improvements to DCP reading compatibility for different flows
within Vivado
API Additions:
- com.xilinx.rapidwright.bitstream.BitLocation "public int hashCode()"
- com.xilinx.rapidwright.bitstream.BitLocation "public boolean equals(Object obj)"
- com.xilinx.rapidwright.bitstream.Bitstream "public static Bitstream readBitstream(Path fileName)"
- com.xilinx.rapidwright.bitstream.Block "public int getBit(BitLocation bit, Tile tile)"
- com.xilinx.rapidwright.bitstream.Block "public boolean updateBit(BitLocation bit, Tile tile, int value, Block golden)"
- com.xilinx.rapidwright.bitstream.ConfigRow "public ConfigRow(int configRowIdx)"
- com.xilinx.rapidwright.bitstream.FAR "public Block getConfigBlock(int slrCfgOrder)"
- com.xilinx.rapidwright.bitstream.Packet "public int hashCode()"
- com.xilinx.rapidwright.bitstream.Packet "public boolean equals(Object obj)"
- com.xilinx.rapidwright.design.Cell "public static final String FF_ROUTETHRU_TYPE"
- com.xilinx.rapidwright.design.Cell "public Cell getReferenceCopy()"
- com.xilinx.rapidwright.design.Cell "public boolean isFFRoutethruCell()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalNetsRouting()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalNetsRouting(boolean copyOrigNets)"
- com.xilinx.rapidwright.design.Design "public Map<String, List> getOriginalNetRouting()"
- com.xilinx.rapidwright.design.Design "public boolean isCopyingOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Design "public void setCopyingOriginalSiteInsts(boolean copyOrigSiteInsts)"
- com.xilinx.rapidwright.design.Design "public Map<String, SiteInst> getOriginalSiteInsts()"
- com.xilinx.rapidwright.design.Net "public List getCopyOfPIPs()"
- com.xilinx.rapidwright.design.SiteInst "public void addPin(SitePinInst sitePinInst)"
- com.xilinx.rapidwright.design.SiteInst "public SiteInst getReferenceCopy()"

Assets 9

24 Jul 22:49

clavin-xlnx

v2023.1.2-beta

92eb05d

RapidWright 2023.1.2-beta Release

Release Notes:

Shell creation improvements to enable lock_design and timing closure preservation (#760)
Adds a MakeBlackBox command line tool (#747)
Removes the VCC A6 pin on 5LUT usages when removing cells (#741)
Add DesignTools.getAllRoutedSitePinsFromPhysicalPin() (#755)
Correctly update dual-output route flags when unrouting (#737)
[PhysNetlistReader] Set cell type of LOCKED cells (#767)
Updates RAM32X1S property to correct default (#751)
[Interchange] PhysNetlistReader to create STATIC_SOURCE SiteInsts (#766)
RWRoute Fixes (#765)
GlobalSignalRouting.routeStaticNet() to create output SPIs (#761)
DesignTools.createCeSrRstPinsToVCC() to skip non-SLICE FFs (#744)
[PartialRouter] Improve incremental global routing (#759)
GlobalSignalRouting fixes for routing to non clock-pins (#757)
DesignTools.makePhysNetNamesConsistent() to merge static nets too (#753)
[UltraScaleClockRouting] Reset RouteNode.parent (#752)
Created parameterizable counter with an adder as a submodule (#713)
[RWRoute] Fix PartialRouter for when clk node already unpreserved (#746)
[Interchange] Fix PhysicalNetlist's MultiCellPinMapping (#743)
Unroute site routing when removing a cell (#729)
PartialRouter's global router to not unpreserve sink nodes (#736)
DesignTools.makePhysNetNamesConsistent() to use hier name (#735)
DesignTools.makePhysNetNamesConsistent() to consider */<const{0,1}> (#734)
Add DcpToInterchange class (#704)
Add compile step (#733)
Add EdifToLogicalNetlist to MainEntrypoint (#731)
Fix Javadoc warnings (#723)
Fixes an issue with makeBlackBox trying to remove pins from renamed nets (#728)
[PhysNetlistReader] Set Cell type for routethru cells (#727)
Multilevel macro expansion (#726)
TestReplaceEDIFInDCP to copy DCP before replacing in-place (#725)
DesignTools.createMissingSitePinInsts() to skip node-less site pins (#724)
Fix to create alternate source pins on dual output nets.
Fixes incorrect Versal SLR corner tile entries
Cell.getProperty() returns null if no EDIFCellInst found
Cell.getAllSitePinsFromLogicalPin() to not return any null pins
Cell.getAllCorrespondingSitePinNames() to not NPE if no physical pin mapping
Cell.getCorrespondingSitePinName() to consider F?MUX routethrus
API Additions:
- com.xilinx.rapidwright.device.PIP "public boolean isLogicalDriver()"
- com.xilinx.rapidwright.design.Cell "public String getCorrespondingSitePinName(String logicalPinName, String physPinName, List siteWires)"

Assets 9

21 Jun 22:06

clavin-xlnx

v2023.1.1-beta

802345b

RapidWright 2023.1.1-beta Release

Release Notes:

UltraScale Incremental Clock Router Improvements (#540)
Adds VivadoTools, a Vivado wrapper/helper in RapidWright (#684)
Fixes published Maven Central jar (#698)
Enhancements to RWRoute (#691, #696)
Interchange reader/writer improvements (#677)
Fix for issue #709
Improves handling of site routing and site pins when updating
physical netlist

Assets 9

01 Jun 17:12

clavin-xlnx

v2023.1.0-beta

cefe09a

RapidWright 2023.1.0-beta Release

Release Notes:

Support for Vivado 2023.1 devices and reading 2023.1 DCPs
Full adoption of Zstandard compression for all device and data
files - 11% faster device loads and 108% faster device cache loads with file size reductions of 32% and 52% respectively.
Has a new 'rapidwright' run wrapper that avoids the need to set CLASSPATH, provides convenience to run any class file with a main() method, run the Jython interpreter and enables one-liner Jython commands. Run rapidwright at the prompt for more details.
Fix duplicate net source pins (won't set the alternate source if it is the same as the source)
Change Net.connect() behavior to connect to existing SitePinInst if net is null
DesignTools.createCeSrRstPinsToVCC() to detect gnd to invert (#664)
EDIFNetlist.cellInstIOStandardFallback to collect set of IOSTANDARDs instead of throwing an error if there is a conflict (#671)
[EDIF] More expanded macros to be deep copied from prim library (#672)
Ignore TestCheckOpenFilesInstalled.test if outside of gradle (#674)
[EDIF] EDIFNetlist.collapseMacroUnisims() to not clobber cell (#675)
[EDIF] Explicit DEFAULT IOStandard on Cell to be overriden by Net (#686)
API Additions:
- (None)
API Deprecation Removals (--> Replacements) [Closed Source]:
- com.xilinx.rapidwright.device.Tile "public String getNameRoot() --> "public string getRootName()"
- com.xilinx.rapidwright.device.Device "public Tile[][] getTilesByNameRoot(String nameRoot)" --> "getTilesByRootName(String rootName)"

Assets 9

03 May 21:32

clavin-xlnx

v2022.2.3-beta

368002d

RapidWright 2022.2.3-beta Release

NOTE: Due to GitHub size limitations, All Series7 devices are now located in rapidwright_data2.zip. All other files are in rapidwright_data.zip.

Release Notes:

Adds preliminary support for Zstandard compression. Uses it in device cache file generation. Next release will use it for all data files.
Fixes an issue with missing Versal Premium families unisim data (#631)
Adds an option to the Interchange device model writer to exclude routing info. to enable placement of the largest devices (#658)
Fixes an issue in the PBlockGenerator parser (#633)
Resolves an issue where collapsed macro ports' parent reference was not set properly (#654)
EDIFNetlist.getIOStandard() to inherit IOStandard from EDIFNet (#646)
API Additions:
- com.xilinx.rapidwright.design.Design "public static boolean readEdifAndXdefInParallel()"
- com.xilinx.rapidwright.design.Design "public static void setReadEdifAndXdefInParallel(boolean readEdifAndXdefInParallel)"

Assets 10

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