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STM32: Fix system clock setup for XTAL and/or internal source on STM32H743 #13640

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merged 2 commits into from
Sep 23, 2020
Merged

STM32: Fix system clock setup for XTAL and/or internal source on STM32H743 #13640

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3f83163
Fixed system clock setup for XTAL and/or internal source on stm32f743…
isaev-d Sep 20, 2020
8597f6a
Removed excess space simbol. Also runtime config check changed to com…
isaev-d Sep 21, 2020
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14 changes: 11 additions & 3 deletions targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H743xI/TARGET_NUCLEO_H743ZI2/system_clock.c
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Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,7 @@ void SetSysClock(void)
}
}


#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
Expand All @@ -109,11 +110,18 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
}
#if HSE_VALUE==8000000
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
#elif HSE_VALUE==25000000
RCC_OscInitStruct.PLL.PLLM = 5; // 5 MHz
RCC_OscInitStruct.PLL.PLLN = 192; // 960 MHz
#else
#error Unsupported externall clock value, check hse_value define
#endif
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 4; // 2 MHz
RCC_OscInitStruct.PLL.PLLN = 480; // 960 MHz
RCC_OscInitStruct.PLL.PLLP = 2; // PLLCLK = SYSCLK = 480 MHz
RCC_OscInitStruct.PLL.PLLQ = 96; // PLL1Q used for FDCAN = 10 MHz
RCC_OscInitStruct.PLL.PLLR = 2;
Expand Down Expand Up @@ -178,7 +186,7 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
RCC_OscInitStruct.PLL.PLLN = 100;
RCC_OscInitStruct.PLL.PLLN = 120;
RCC_OscInitStruct.PLL.PLLP = 2;
RCC_OscInitStruct.PLL.PLLQ = 2;
RCC_OscInitStruct.PLL.PLLR = 2;
Expand Down