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README.md
README.md
 
 
barrel.v
barrel.v
 
 
cla.v
cla.v
 
 
fadd.v
fadd.v
 
 
mux.v
mux.v
 
 
rca.v
rca.v
 
 
shift_registor.v
shift_registor.v
 
 
testbench.v
testbench.v
 
 
v.sh
v.sh
 
 

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Half Precision Floating Point Representation In Verilog

the file name fadd.v is a half precision FPR adder IEEE 754 Standard Sign Bit 1 Exponant Bit 5 Mantisa Bit 10 th MUX is 16:4 the file barrel shift resistor is of 16 bit the adder used is Ripple Carry Adder

more need to be adder ...

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Half Precision Floating Point Adder in Verilog

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verilog floating-point-adder

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