#STOP-WATCH-AND-RTC-FPGA-FULL-PROJECT

#STOP WATCH AND RTC .

#project conatains : QSYS file and VHD file for using among quartus and uploading to fpga (FPGA: EP2C20F484C7)

#controling : #keys are for controlling stop watch : - key 1 :start - key 2: pause - key 3 : stop and renitialise to 0. #SWITCHES : are for switching between clock mode and STOP WATCH : - SW 0 : STOP WATCH - SW 1 : CLOCK.