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👨🏻‍💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.

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Name		Name	Last commit message	Last commit date
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.vscode		.vscode
Includes		Includes
Resources		Resources
Sources		Sources
Tests		Tests
.gitattributes		.gitattributes
.gitignore		.gitignore
README.md		README.md
Report-single.pdf		Report-single.pdf

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Single-cycle MIPS

45 Instructions
Details
- Logical
  - AND
  - OR
  - XOR
  - NOR
  - ANDI
  - XORI
  - LUI
  - ORI, LI
- Shift
  - SLL, NOP
  - SRL
  - SRA
  - SLLV
  - SRLV
  - SRAV
- Arithmetic
  - ADD[U]
  - SUB[U]
  - SLT[U]
  - ADDI[U]
  - SLTI[U]
- Jump
  - JR
  - JALR
  - J
  - JAL
- Branch
  - BEQ
  - B
  - BGTZ
  - BLEZ
  - BNE
  - BLTZ
  - BLTZAL
  - BGEZ
  - BGEZAL, BAL
- Load / Store
  - LB
  - LBU
  - LH
  - LHU
  - LW
  - SB
  - SH
  - SW

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👨🏻‍💻 Pipelined MIPS I CPU with 49 instructions & multiplication & direct-mapped cache in Verilog.

simulator mips verilog

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