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Squashed 'utils' changes from 9fb2945..4eff91b (#738)
4eff91b Merge pull request Xilinx#292 from tuol/update_dm_name 9b0299c update e8b5b5f Merge pull request Xilinx#291 from tuol/add_perf_doc ca2c56a add perf data of 4d DM f5d6bc9 Merge pull request Xilinx#290 from tuol/fix_dm_doc 4d5056e update doc for 4D datamover 1dc9899 Merge pull request Xilinx#289 from RepoOps/update_readme_5 0e4c644 update 0fc8870 update README 32b471c update README 4ed37e1 Merge pull request Xilinx#288 from tuol/cr_1143159 eeb9c9e add freq constrain c6adb44 Merge pull request Xilinx#287 from tuol/fix_4d 4a65513 add missing utils.mk b5a1c14 Merge pull request Xilinx#286 from tuol/fix_doc_1010 c633178 add missing images 569364b complement rst doc 0ac615d Merge pull request Xilinx#285 from tuol/4d_datamover_l2_case 4d0e9ae add 4D data mover L2 case 398dc24 Merge pull request Xilinx#284 from tuol/cr_1141439 08a1ce1 Merge pull request Xilinx#283 from RepoOps/update_doc_url_3 0ab1937 slightly update L2/script/makefile 7ab5ed0 update url and branch in doc 5c6bfef Merge pull request Xilinx#282 from tuol/fix_doc_version_3 73b7358 update version to 2022.2 6910294 Merge pull request Xilinx#281 from tuol/doc_fix 8595a85 add release note f8d18dd Merge pull request Xilinx#280 from RepoOps/update_makefile_20220908-212141 7d7643c update Makefile with 2.0.8 version Co-authored-by: sdausr <sdausr@xilinx.com>
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43 changes: 43 additions & 0 deletions
43
utils/L2/scripts/templates/datamover/load_4D_cuboid_from_master_to_stream.cpp.j2
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/* | ||
* Copyright 2020 Xilinx, Inc. | ||
* | ||
* Licensed under the Apache License, Version 2.0 (the "License"); | ||
* you may not use this file except in compliance with the License. | ||
* You may obtain a copy of the License at | ||
* | ||
* http://www.apache.org/licenses/LICENSE-2.0 | ||
* | ||
* Unless required by applicable law or agreed to in writing, software | ||
* distributed under the License is distributed on an "AS IS" BASIS, | ||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
* See the License for the specific language governing permissions and | ||
* limitations under the License. | ||
*/ | ||
|
||
#include <stdint.h> | ||
#include "xf_utils_hw/pl_datamover.hpp" | ||
|
||
extern "C" void {{ k["name"] }}({% for m in k["map"] %} | ||
// {{ loop.index0 }} | ||
hls::burst_maxi<ap_uint<64> > {{ m["in_port"]["descriptors"] }}, | ||
hls::burst_maxi<ap_uint<{{ m["out_port"]["width"] }}> > {{ m["in_port"]["name"] }}, | ||
hls::stream<ap_axiu<{{ m["out_port"]["width"] }}, 0, 0, 0> >& {{ m["out_port"]["stream"] }}{{ ',' if loop.index0 != (k["map"] | length) - 1 else '' }} | ||
{% endfor %} | ||
) { | ||
; // clang-format off{% for m in k["map"] %} | ||
#pragma HLS interface m_axi offset=slave bundle=gmem0{{ loop.index0 }} port={{ m["in_port"]["descriptors"] }} \ | ||
max_read_burst_length={{ m["in_port"]["burst_len"] }} num_read_outstanding={{ m["in_port"]["outstanding"] }} latency={{ m["in_port"]["latency"] }} depth = 4096 | ||
#pragma HLS interface m_axi offset=slave bundle=gmem1{{ loop.index0 }} port={{ m["in_port"]["buffer"] }} \ | ||
max_read_burst_length={{ m["in_port"]["burst_len"] }} num_read_outstanding={{ m["in_port"]["outstanding"] }} latency={{ m["in_port"]["latency"] }} depth = 4096 | ||
#pragma HLS interface s_axilite bundle=control port={{ m["in_port"]["descriptors"] }} | ||
#pragma HLS interface s_axilite bundle=control port={{ m["in_port"]["buffer"] }} | ||
#pragma HLS interface axis port={{ m["out_port"]["stream"] }} | ||
{% endfor %} | ||
#pragma HLS interface s_axilite bundle=control port=return | ||
; // clang-format on | ||
|
||
#pragma HLS dataflow | ||
{% for m in k["map"] %} | ||
xf::common::utils_hw::read4D<{{ m["out_port"]["width"] }}, {{ m["in_port"]["latency"] }}, {{ m["in_port"]["outstanding"] }}, {{ m["in_port"]["burst_len"] }}>({{ m["in_port"]["descriptors"] }}, {{ m["in_port"]["buffer"] }}, {{ m["out_port"]["stream"] }}); {% endfor %} | ||
} | ||
{# vim: set filetype=cpp : #} |
43 changes: 43 additions & 0 deletions
43
utils/L2/scripts/templates/datamover/store_4D_cuboid_from_stream_to_master.cpp.j2
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/* | ||
* Copyright 2020 Xilinx, Inc. | ||
* | ||
* Licensed under the Apache License, Version 2.0 (the "License"); | ||
* you may not use this file except in compliance with the License. | ||
* You may obtain a copy of the License at | ||
* | ||
* http://www.apache.org/licenses/LICENSE-2.0 | ||
* | ||
* Unless required by applicable law or agreed to in writing, software | ||
* distributed under the License is distributed on an "AS IS" BASIS, | ||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
* See the License for the specific language governing permissions and | ||
* limitations under the License. | ||
*/ | ||
|
||
#include <stdint.h> | ||
#include "xf_utils_hw/pl_datamover.hpp" | ||
|
||
extern "C" void {{ k["name"] }}({% for m in k["map"] %} | ||
// {{ loop.index0 }} | ||
hls::burst_maxi<ap_uint<64> > {{ m["in_port"]["descriptors"] }}, | ||
hls::stream<ap_axiu<{{ m["in_port"]["width"] }}, 0, 0, 0> >& {{ m["in_port"]["stream"] }}, | ||
hls::burst_maxi<ap_uint<{{ m["in_port"]["width"] }}> > {{ m["out_port"]["buffer"] }}{{ ',' if loop.index0 != (k["map"] | length) - 1 else '' }} | ||
{% endfor %} | ||
) { | ||
; // clang-format off{% for m in k["map"] %} | ||
#pragma HLS interface m_axi offset=slave bundle=gmem0{{ loop.index0 }} port={{ m["in_port"]["descriptors"] }} \ | ||
max_read_burst_length={{ m["out_port"]["burst_len"] }} num_read_outstanding={{ m["out_port"]["outstanding"] }} latency={{ m["out_port"]["latency"] }} depth = 4096 | ||
#pragma HLS interface m_axi offset=slave bundle=gmem1{{ loop.index0 }} port={{ m["out_port"]["buffer"] }} \ | ||
max_read_burst_length={{ m["out_port"]["burst_len"] }} num_read_outstanding={{ m["out_port"]["outstanding"] }} latency={{ m["out_port"]["latency"] }} depth = 4096 | ||
#pragma HLS interface s_axilite bundle=control port={{ m["in_port"]["descriptors"] }} | ||
#pragma HLS interface s_axilite bundle=control port={{ m["out_port"]["buffer"] }} | ||
#pragma HLS interface axis port={{ m["in_port"]["stream"] }} | ||
{% endfor %} | ||
#pragma HLS interface s_axilite bundle=control port=return | ||
; // clang-format on | ||
|
||
#pragma HLS dataflow | ||
{% for m in k["map"] %} | ||
xf::common::utils_hw::write4D<{{ m["in_port"]["width"] }}, {{ m["out_port"]["latency"] }}, {{ m["out_port"]["outstanding"] }}, {{ m["out_port"]["burst_len"] }}>({{ m["in_port"]["descriptors"] }}, {{ m["in_port"]["stream"] }}, {{ m["out_port"]["buffer"] }});{% endfor %} | ||
} | ||
{# vim: set filetype=cpp : #} |
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kernel/*.cpp | ||
kernel/*.inc | ||
_krnlgen |
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