SC/SCD don't adjust for C0

[bacam]

The standard MIPS store conditional instructions aren't adjusted by the default data capability, C0 (or checked against, it appears). For example, with an unaligned base for C0 and matching address in $2:

CapReg 0 <- t:1 s:0 perms:0x7fffffff type:0x000000 offset:0x0000000000000000 base:0x0000000000000001 length:0xfffffffffffffffe
Reg 2 <- 0x000000004000100f

The L3 model manages a linked load / store conditional

instr 0 805 00000000400007fc : c0410000   ll          $1, 0($2)
Load of 4 byte(s) from vAddr 0x0000000040001010
Reg 1 <- 0x0000000000000000
instr 0 806 0000000040000800 : e0410000   sc          $1, 0($2)
Store 0x0000000000000000, mask 0xffffffff00000000 (4 byte(s)) at vAddr 0x0000000040001010

whereas qemu raises an exception for an unaligned load on the sc

0x00000000400007fc:  ll at,0(v0)
    Write at = 0000000000000000
    Write LLAddr = 0000000004000101
0x0000000040000800:  sc at,0(v0)
mips_cpu_do_interrupt enter: PC 0000000040000800 EPC b66f68a40e1e6de8 address error store exception
    Write BadVAddr = 000000004000100f

[michael-roe]

The problem is the check for the address being aligned.

I have added a regression test to the test suite (test_cp2_c0_sc).

[bacam]

It affects the calculated address, too. If I increase the base of C0 to 4, then L3 still does the store

instr 0 806 0000000040000804 : e0410000   sc          $1, 0($2)
Store 0x1000000000000000, mask 0xffffffff00000000 (4 byte(s)) at vAddr 0xffffffffbfc00420
Reg 1 <- 0x0000000000000001

but qemu rejects it:

0x0000000040000804:  sc at,0(v0)
    Write at = 0000000000000000

[staceyson]

The change ad3454e fixes this and test_cp2_c0_sc now passes.