Breaking Changes Wishlist

[Cydhra]

Listed here are breaking changes to implement if a major version release is planned

• Rename FastRmq to SmallRmq or something similar, expressing its higher memory efficiency
• Rename BinaryRmq to SparseRmq
• Change return value of count_ones and count_zeros functions in both bit vectors to usize
• Refactor the data structure APIs into traits, so alternative backing structs can be used interchangeably with trait objects, and code can be reused when providing alternative implementations or utility like MaskedBitVec. This also enables a graceful implementation of Zero-Copy Serialization/Deserialization #5
• Rename BitVector::from_bits to from_bits_u8
• Change the Vecs inside immutable data structures into Box<&[u64]> where applicable
• Change u64 limbs into a struct worth 512 bits to force both cache-alignment and avx-alignment
• merge superblocks and blocks into a cache-aligned interleaved structure to reduce cache misses
• Maybe abstract over the RS support structure, such that it can be exchanged through different implementations
• Change RsVec fields (and fields of the supporting structs) that are not indices from usize to u64 (like len, rank0, ...)