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✅Mature Cortex-R5 support added
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@EDI-Systems
EDI-Systems committed Mar 10, 2018
1 parent 4032982 commit 6a662cd
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Showing 12 changed files with 170 additions and 113 deletions.
26 changes: 17 additions & 9 deletions MProkaron/Benchmark/Platform/test_TMS570LC4357.h
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Expand Up @@ -12,10 +12,10 @@ Description : The testbench for TMS570LC4357.

/* Defines *******************************************************************/
/* Where are the initial stacks */
#define THD1_STACK (&Stack_1[230])
#define THD2_STACK (&Stack_2[230])
#define THD1_STACK (&Stack_1[215])
#define THD2_STACK (&Stack_2[215])
/* How to read counter */
#define COUNTER_READ() (0)
#define COUNTER_READ() ((rtiREG1->CNT[0].FRCx)<<3)
/* Are we testing the memory pool? */
#define TEST_MEM_POOL 8192
/* Are we doing minimal measurements? */
Expand All @@ -40,8 +40,8 @@ Return : None.
******************************************************************************/
void Timer_Init(void)
{
/* TIM2 clock = 1/2 CPU clock */

/* RTI/FRC0 clock = 1/8 CPU clock, already initialized. Disable compare 1 */
rtiREG1->INTFLAG = 2U;
}
/* End Function:Timer_Init ***************************************************/

Expand All @@ -54,12 +54,18 @@ Return : None.
******************************************************************************/
void Int_Init(void)
{
/* TIM4 clock = 1/2 CPU clock */

/* RTI/FRC1 clock = 1/8 CPU clock */
rtiREG1->INTFLAG = 2U;
rtiStopCounter(rtiREG1, rtiCOUNTER_BLOCK1);
rtiSetPeriod(rtiREG1, rtiCOMPARE1, 3750);
rtiEnableNotification(rtiREG1, rtiNOTIFICATION_COMPARE1);
rtiStartCounter(rtiREG1, rtiCOUNTER_BLOCK1);
}
volatile int Acc_Count=0;
/* The interrupt handler */
void TIM4_IRQHandler(void)
void rtiInterrupt(void)
{
Acc_Count++;
Int_Handler();
}
/* End Function:Int_Init *****************************************************/
Expand All @@ -73,7 +79,9 @@ Return : None.
******************************************************************************/
void Int_Disable(void)
{
/* Disable timer 4 interrupt */
/* Disable channel 1 interrupt */
rtiDisableNotification(rtiREG1, rtiNOTIFICATION_COMPARE1);
rtiStopCounter(rtiREG1, rtiCOUNTER_BLOCK1);
}
#endif
/* End Function:Int_Disable **************************************************/
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13 changes: 12 additions & 1 deletion MProkaron/Include/Platform/CortexR/Chips/TMS570LC4357/platform_TMS570LC4357.h
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Expand Up @@ -10,6 +10,8 @@ Description: The configuration file for TMS570LC4357.
/* The HAL library */
#include "HL_sys_common.h"
#include "HL_system.h"
#include "HL_rti.h"
#include "HL_sci.h"

/* The maximum number of preemption priority levels in the system.
* This parameter must be divisible by the word length - 32 is usually sufficient */
Expand All @@ -21,23 +23,32 @@ Description: The configuration file for TMS570LC4357.
/* Are we using custom hooks? */
#define RMP_USE_HOOKS RMP_FALSE
/* The stzck size of the init thread */
#define RMP_INIT_STACK_SIZE 256
#define RMP_INIT_STACK_SIZE 1024
/* The mask/unmask interrupt operations */
#define RMP_MASK_INT() RMP_Disable_Int()
#define RMP_UNMASK_INT() RMP_Enable_Int()

#define RMP_CRX_SYSTICK_VAL 3750

/* Other low-level initialization stuff - clock and serial */
#define RMP_CRX_LOW_LEVEL_INIT() \
do \
{ \
/* The TI library is in charge of all the initialization of interrupts and clocks */\
rtiInit(); \
rtiSetPeriod(rtiREG1, rtiCOMPARE0, RMP_CRX_SYSTICK_VAL); \
rtiEnableNotification(rtiREG1, rtiNOTIFICATION_COMPARE0); \
rtiStartCounter(rtiREG1, rtiCOUNTER_BLOCK0); \
/* Enable SCI */ \
sciInit(); \
} \
while(0)

/* This is for debugging output */
#define RMP_CRX_PUTCHAR(CHAR) \
do \
{ \
sciSendByte(sciREG1,(CHAR)); \
} \
while(0)
/* End Defines ***************************************************************/
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27 changes: 18 additions & 9 deletions MProkaron/Include/Platform/CortexR/platform_crx.h
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Expand Up @@ -138,15 +138,24 @@ typedef s32 ret_t;
#define RMP_CMX_SHCSR_MEMFAULTENA (1<<16)
/* MPU definitions */
#define RMP_CMX_MPU_PRIVDEF 0x00000004
/* NVIC definitions */
#define RMP_CMX_NVIC_GROUPING_P7S1 0
#define RMP_CMX_NVIC_GROUPING_P6S2 1
#define RMP_CMX_NVIC_GROUPING_P5S3 2
#define RMP_CMX_NVIC_GROUPING_P4S4 3
#define RMP_CMX_NVIC_GROUPING_P3S5 4
#define RMP_CMX_NVIC_GROUPING_P2S6 5
#define RMP_CMX_NVIC_GROUPING_P1S7 6
#define RMP_CMX_NVIC_GROUPING_P0S8 7

/* Mode definitions */
#define RMP_CRX_SYS (0x1F)
#define RMP_CRX_USR (0x10)
#define RMP_CRX_SVC (0x13)
#define RMP_CRX_IRQ (0x12)
#define RMP_CRX_FIQ (0x11)
#define RMP_CRX_ABT (0x17)
#define RMP_CRX_UND (0x1B)

/* CPSR bit definitions */
#define RMP_CRX_CPSR_E (1<<9)
#define RMP_CRX_CPSR_A (1<<8)
#define RMP_CRX_CPSR_I (1<<7)
#define RMP_CRX_CPSR_F (1<<6)
#define RMP_CRX_CPSR_T (1<<5)
#define RMP_CRX_CPSR_M(X) ((X))

/* Fault definitions */
/* The NMI is active */
#define RMP_CMX_ICSR_NMIPENDSET (((ptr_t)1)<<31)
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35 changes: 25 additions & 10 deletions MProkaron/Platform/CortexR/platform_crx.c
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Expand Up @@ -36,7 +36,7 @@ Return : None.
Other : When the system stack safe redundancy is set to zero, the stack
looks like this when we try to step into the next process by
context switch:
HIGH--> XPSR PC LR(1) R12 R3-R0 LR R11-R4 -->LOW
HIGH--> CPSR PC LR R12-R0 -->LOW
We need to set the stack correctly pretending that we are
returning from an systick timer interrupt. Thus, we set the XPSR
to avoid INVSTATE; set PC to the pseudo-process entrance; set LR
Expand All @@ -45,15 +45,30 @@ Other : When the system stack safe redundancy is set to zero, the stack
******************************************************************************/
void _RMP_Stack_Init(ptr_t Entry, ptr_t Stack, ptr_t Arg)
{
/* The "9" here is because we also pushed other registers to PSP */
/* This is the LR value indicating that we never used the FPU */
((ptr_t*)Stack)[0+8]=0xFFFFFFFD;
/* CM3:Pass the parameter */
((ptr_t*)Stack)[0+9]=Arg;
/* CM3:for xPSR. fill the T bit,or an INVSTATE will happen */
((ptr_t*)Stack)[6+9]=Entry;
/* CM3:Set the process entrance */
((ptr_t*)Stack)[7+9]=0x01000200;
ptr_t* Stack_Ptr;

Stack_Ptr=(ptr_t*)Stack;
Stack_Ptr[0]=Arg;
Stack_Ptr[1]=0x01010101;
Stack_Ptr[2]=0x02020202;
Stack_Ptr[3]=0x03030303;
Stack_Ptr[4]=0x04040404;
Stack_Ptr[5]=0x05050505;
Stack_Ptr[6]=0x06060606;
Stack_Ptr[7]=0x07070707;
Stack_Ptr[8]=0x08080808;
Stack_Ptr[9]=0x09090909;
Stack_Ptr[10]=0x10101010;
Stack_Ptr[11]=0x11111111;
Stack_Ptr[12]=0x12121212;
Stack_Ptr[13]=0x14141414;
Stack_Ptr[14]=Entry;

/* See if the user code is thumb or ARM */
if((Entry&0x01)!=0)
Stack_Ptr[15]=RMP_CRX_CPSR_E|RMP_CRX_CPSR_A|RMP_CRX_CPSR_F|RMP_CRX_CPSR_T|RMP_CRX_CPSR_M(RMP_CRX_SYS);
else
Stack_Ptr[15]=RMP_CRX_CPSR_E|RMP_CRX_CPSR_A|RMP_CRX_CPSR_F|RMP_CRX_CPSR_M(RMP_CRX_SYS);
}
/* End Function:_RMP_Stack_Init **********************************************/

Expand Down
76 changes: 39 additions & 37 deletions MProkaron/Platform/CortexR/platform_crx_asm.asm
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Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@
;---------------------------------------------------------------
; CPSR CPSR CPSR CPSR CPSR CPSR
; SPSR_F SPSR_S SPSR_A SPSR_I SPSR_U
; 10000 10001 10011 10111 10010 11011
; 11111/10000 10001 10011 10111 10010 11011
;---------------------------------------------------------------
;R0-R7 : General purpose registers that are accessible
;R8-R12 : General purpose regsisters that are not accessible by 16-bit thumb
Expand Down Expand Up @@ -57,14 +57,11 @@
;The PendSV trigger
.global _RMP_Yield
;The system pending service routine
.global _svc ;PendSV_Handler
.global ssiInterrupt ;PendSV_Handler
;The systick timer routine
.global SysTick_Handler
.global rtiNotification ;SysTick_Handler
;Other unused error handlers
.global _dabort
.global _prefetch
.global _undef
.global phantomInterrupt
.global phantomInterrupt
;/* End Exports **************************************************************/

;/* Begin Imports ************************************************************/
Expand Down Expand Up @@ -145,14 +142,17 @@ RMP_MSB_Get .asmfunc
_RMP_Yield .asmfunc
PUSH {R0-R1}
SVC #0 ;Trigger the SVC instruction
LDR R0,SSI1_Addr ;The SSI interrupt register address
MOVS R1,#0x7500 ;The key needed to trigger such interrupt
STR R1,[R0] ;Trigger the software interrupt

DSB ;Data and instruction barrier
ISB
POP {R0-R1}
BX LR
.endasmfunc
.endasmfunc
SSI1_Addr .word 0xFFFFFFB0
;/* End Function:_RMP_Yield **************************************************/

;/* Begin Function:_RMP_Start *************************************************
Expand All @@ -166,7 +166,7 @@ _RMP_Start .asmfunc
;Should never reach here
SUBS R1,R1,#64 ;This is how we push our registers so move forward
MOVS SP,R1 ;Set the stack pointer
BL R0 ;Branch to our target
BLX R0 ;Branch to our target
Loop: B Loop ;Capture faults
.endasmfunc
;/* End Function:_RMP_Start **************************************************/
Expand All @@ -182,28 +182,34 @@ Loop: B Loop ;Capture faults
;Input : None.
;Output : None.
;*****************************************************************************/
_svc
ssiInterrupt .asmfunc
.endasmfunc
PendSV_Handler .asmfunc
; MRS R0,PSP ;Spill all the registers onto the user stack
STMDB R0!,{R4-R11,LR}
SUBS LR,LR,#0x04 ;Correct the LR value first - the LR is always a word behind
SRSDB SP!,#0x1F ;Save LR at SVC(PC at SYS) and SPSR at SVC(CPSR at SYS)
CPS #0x1F ;Switch to SYS mode
PUSH {R0-R12,LR} ;Spill all registers to stack
LDR R0,SSIF_Addr ;Clear the software interrupt flag
MOV R1,#0x0F
STR R1,[R0]

BL RMP_Save_Ctx ;Save extra context
; LDR R1,=RMP_Cur_SP ;Save The SP to control block.
STR R0,[R1]
LDR R1,RMP_Cur_SP_Addr ;Save The SP to control block.
STR SP,[R1]
BL _RMP_Get_High_Rdy ;Get the highest ready task.
; LDR R1,=RMP_Cur_SP ;Load the SP.
LDR R0,[R1]
LDR R1,RMP_Cur_SP_Addr ;Load the SP.
LDR SP,[R1]
BL RMP_Load_Ctx ;Load extra context

LDMIA R0!,{R4-R11,LR}
; MSR PSP,R0
BX LR ;The LR will indicate whether we are using FPU.
.endasmfunc
POP {R0-R12,LR}
RFEIA SP!
.endasmfunc
SSIF_Addr .word 0xFFFFFFF8
;/* End Function:PendSV_Handler **********************************************/

;/* Begin Function:SysTick_Handler ********************************************
Expand All @@ -214,30 +220,26 @@ PendSV_Handler .asmfunc
; can make way around this problem.
; However, if your compiler support inline assembly functions, this
; can also be written in C.
; In the TI library, this was called by a high-level C function, thus the
; SRSDB and RFEIA are not needed.
;Input : None.
;Output : None.
;*****************************************************************************/
rtiNotification .asmfunc
.endasmfunc
SysTick_Handler .asmfunc
PUSH {LR}
;SRSDB SP!,#0x1F ;Save LR at SVC(PC at SYS) and SPSR at SVC(CPSR at SYS)
PUSH {R0-R3,LR}
MOVS R0,#0x01 ;We are not using tickless.
MOVS R0,#0x01 ;We are not using tickless.
BL _RMP_Tick_Handler
POP {PC}
.endasmfunc
;/* End Function:SysTick_Handler *********************************************/

_dabort .asmfunc
B _dabort
.endasmfunc

_prefetch .asmfunc
B _prefetch
POP {R0-R3,PC}
;RFEIA SP!
.endasmfunc
;/* End Function:SysTick_Handler *********************************************/

_undef .asmfunc
B _undef
.endasmfunc
RMP_Cur_SP_Addr .word RMP_Cur_SP

phantomInterrupt .asmfunc
B phantomInterrupt
Expand Down
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