ConstrastEQ is a VHDL module of a contrast equalizer to be implemented on FPGAs. A contrast equalizer is a module that maximizes contrast in images by taking the minimum and maximum pixel values and making them 0 and 255 respectively, scaling all other pixels' values accordingly.

This project was made as an assignment of Logic Networks' course (2020/2021), and consisted in the design and implementation of a module in VHDL language starting from a specification in natural language of its behaviour. The following is a finite state machine schema, describing the behavior of the module:

A detailed explanation of how the module works and how it was tested is in the doc folder, in Report_reti_logiche.pdf. Unfortunately the report had to be written in italian, we suggest the use of automatic translation tools.

Authors

• Elia Fantini
• Mauro Famà

How to use

The file retilogiche.vhd in the code folder has to be opened by the software Xilinx Vivado or similar softwares and has to be synthetized on a FPGA. For our tests, we used a simulated xc7a200tfbg484-1 FPGA.

Contents

• In the code folder there is the code written in VHDL language of the implemented module and two testbench.
• The documentation (in italian) of the project is in the doc folder.
• In the spec folder there are the specifications and project rules provided by the teachers (in italian).

🛠 Skills

VHDL language. Usage of Xilinx Vivado software, testing and benchmarking of the final module.

🔗 Links